parMERASA -- Multi-core Execution of Parallelised Hard Real-Time Applications Supporting Analysability

Ungerer, Theo; Bradatsch, Christian; Gerdes, Mike; Kluge, Florian; Jahr, Ralf; Mische, Jörg; Fernandes, João Paulo; Zaykov, Pavel; Petrov, Zlatko; Böddeker, Bert; Kehr, Sebastian; Regler, Hans; Hugl, Andreas; Rochange, Christine; Ozaktas, Haluk; Cassé, Hugues; Bonenfant, Armelle; Sainrat, Pascal; Broster, Ian; Lay, Nick; George, David; Quiñones, Eduardo; Panic, Milos; Abella, Jaume; Cazorla, Francisco J.; Uhrig, Sascha; Rohde, Mathias; Pyka, Arthur

doi:10.1109/dsd.2013.46

Cited by 48 publications

(38 citation statements)

References 8 publications

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“…The FP-7 project MERASA (Multi-Core Execution of Hard Real-Time Applications Supporting Analysability) [24] investigated a bus-based CMP with a multi-threaded version of the TriCore processor. The memory hierarchy issue for real-time systems was attacked by a dynamic instruction scratchpad [14].…”

Section: B Merasamentioning

confidence: 99%

Is time predictability quantifiable?

Schoeberl

2012

2012 International Conference on Embedded Computer Systems (SAMOS)

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Abstract-Computer architects and researchers in the realtime domain start to investigate processors and architectures optimized for real-time systems. Optimized for real-time systems means time predictable, i.e., architectures where it is possible to statically derive a tight bound of the worst-case execution time.To compare different approaches we would like to quantify time predictability. That means we need to measure time predictability. In this paper we discuss the different approaches for these measurements and conclude that time predictability is practically not quantifiable. We can only compare the worst-case execution time bounds of different architectures.

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Section: B Merasamentioning

confidence: 99%

Is time predictability quantifiable?

Schoeberl

2012

2012 International Conference on Embedded Computer Systems (SAMOS)

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“…While OTAWA extracts the control flow graph (CFG) from the binary code (thus, performing static timing analysis), RapiTime uses the extracted traces to estimate the WCET by measurements/simulations of the target hardware. Further, the Merasa project was continued on a new action: parMerasa [10,11].…”

Section: Introductionmentioning

confidence: 99%

On the Computation of the WCET for LEON3 and MIPS Processors

Green¹,

Maciel²,

Vargas³

et al. 2017

Seventh International Conference on Advances in Computing, Control and Networking - ACCN 2017

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Abstract-In the last two decades, the worst-case execution time (WCET) bound computation was a topic mainly related with hard real-time systems for aerospace and defense applications. Recently, however, it has become crucial in other domains dealing with timing guarantees. This includes among others, the automotive industry, where V2V and V2X applications for autonomous vehicles are demanding not only fault-tolerant responsiveness, but also the guarantee that timing deadlines will not be violated. In this sense, it is a mandatory condition to have an accurate determination of the WCET parameter in order to guarantee the hard-real time response of these critical systems to the environment. We propose in this paper a method to bound WCET for workloads running in the LEON3 and MIPS architectures. This approach performs a static timing analysis of the application code and based on the IPET technique, bounds the WCET. In addition to the use of the IPET technique, the proposed approach also takes advantage of commercial, opensource tools such as GraphViz and lp_solve to produce a WCET upper bound.

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“…parMERASA is an extension of the MERASA project. It suggests a Tdma-like approach to analyzing timing behavior of multi-core systems [28]. The probabilistic execution time analysis provides an execution time distribution of the application instead of providing a single Wcet value.…”

Section: Related Workmentioning

confidence: 99%

Measurement based WCET Analysis for Multi-core Architectures

Shah

Coombes

Raabe

et al. 2014

Proceedings of the 22nd International Conference on Real-Time Networks and Systems

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The interference on shared resources caused by concurrently executing applications unpredictably prolongs their execution. Hence, determination of the Worst Case Execution Time (Wcet) of applications executing on shared memory multi-core processors is hard to estimate. This hinders the adoption of Commercial Off The Shelf (Cots) multicore processors in hard real-time systems. The existing techniques opt for tailored multi-core architectures to provide high computation power at predictable execution time. However, this approach yields poor resource utilization and high costs. In this paper, we present a technique to measure the Wcet of applications on multi-core architectures using existing measurement based timing analysis tools. Our technique has a minor area impact (≈ 5%). However, this impact is limited to the emulation devices only and production chips remain unchanged. Thus, our technique does not impact performance of the Cots chips by any ways. The technique is demonstrated by measuring Wcet of benchmark applications using the RapiTime timing analysis tool. The tests are conducted on a quad-core NIOS II processor on an Altera Fpga.

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parMERASA -- Multi-core Execution of Parallelised Hard Real-Time Applications Supporting Analysability

Cited by 48 publications

References 8 publications

Is time predictability quantifiable?

Is time predictability quantifiable?

On the Computation of the WCET for LEON3 and MIPS Processors

Measurement based WCET Analysis for Multi-core Architectures

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