Partial Bus-Invert Bus Encoding Schemes for Low-Power DSP Systems Considering Inter-wire Capacitance

Murgan, T.; Bacinschi, P. B.; Ortiz, Alberto García; Glesner, Manfred

doi:10.1007/11847083_17

Cited by 5 publications

(5 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It is able to reduce the transition activity, but it is not able to fully exploit the larger opportunities offered by the signal with t MSB = 0.1. A combination of Bus-Invert with non-redundant memoryless coding [4] is advisable.…”

Section: Resultsmentioning

confidence: 99%

“…Further on, a wide range of approaches have been developed to improve the performance of the basic Bus-Invert scheme. Several approaches referred as Partial Bus-Invert advocate for coding a part of the bus only (see [7], [4] and reference there), while other techniques combine Bus-Invert with other schemata as non-redundant memoryless coding [4] or even more complex approaches as Berger codes [1]. Without a suitable mathematical analysis of the different coding techniques (and their alternatives) it is not possible to exploit them early in the design flow.…”

Section: Introductionmentioning

confidence: 99%

“…Low-power coding for on-chip and off-chip interconnects is emerging [1], [2], [3], [4] as an important technique for overcoming the increasing power budgets required for the communication architecture of modern chips. As technology shrinks, the impact of the interconnects in the overall system power and system performance is increasing.…”

Section: Introductionmentioning

confidence: 99%

“…[3]. Initially, the technique was designed to address the switching activity only, however, several extensions as Odd/Even Bus-Invert have been proposed for reducing the coupling activity as well (see [6], [4] and references there). Further on, a wide range of approaches have been developed to improve the performance of the basic Bus-Invert scheme.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Analysis of Bus-Invert coding in the presence of correlations

García-Ortiz¹,

Gregorek²,

Osewold³

2011

2011 Saudi International Electronics, Communications and Photonics Conference (SIECPC)

View full text Add to dashboard Cite

The selection of the right low-power coding technique during the design of the interconnect architecture has a high potential. However, it requires the analysis and evaluation to be performed at high-levels of abstraction. Closed formulas to quantify the power reduction achieved by each low-power code are therefore highly desirable. Using a simplified Dual Bit Type model for the underlying signals, the current work provides closed formulas for calculating the transition activity of correlated DSP signals encoded with the Bus-Invert technique. It considers the effect of the temporal and spatial correlation present in typical DSP signals. The accuracy of the proposed formulas is validated with extensive simulations at the bit level.

show abstract

Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Analysis of Bus-Invert coding in the presence of correlations

García-Ortiz¹,

Gregorek²,

Osewold³

2011

2011 Saudi International Electronics, Communications and Photonics Conference (SIECPC)

View full text Add to dashboard Cite

show abstract

“…These techniques increase the bit-width of the codewords over the plain data words by one inversion line. Also, application-specific low-power codes, for example for signal processing [9], [13] or address buses [8], [10], [11], were designed. Compared to inversion codes, they are overhead-free (i.e., codeword bit-width equal to dataword bit-width) and/or yield much higher power savings while exhibiting a lower implementation complexity.…”

Section: Related Workmentioning

confidence: 99%

Exploiting Neural-Network Statistics for Low-Power DNN Inference

Bamberg,

Najafi,

Garcia-Ortiz

2024

IEEE Open J. Circuits Syst.

View full text Add to dashboard Cite

Specialized compute blocks have been developed for efficient DNN execution. However, due to the vast amount of data and parameter movements, the interconnects and on-chip memories form another bottleneck, impairing power and performance. This work addresses this bottleneck by contributing a low-power technique for edge-AI inference engines that combines overhead-free coding with a statistical analysis of the data and parameters of neural networks. Our approach reduces the power consumption of the logic, interconnect, and memory blocks used for data storage and movements by up to 80 % for state-of-the-art benchmarks while providing additional power savings for the compute blocks by up to 39 %. These power improvements are achieved with no loss of accuracy and negligible hardware cost.INDEX TERMS Artificial intelligence, edge-AI inference, low-power coding, low-power digital design, neural networks.

show abstract