Partial Dynamic Element Matching Technique for Digital-to-Analog Converters Used for Digital Harmonic-Cancelling Sine-Wave Synthesis

Aluthwala, Pasindu; Weste, N.; Adams, Andrew; Lehmann, Torsten; Parameswaran, Sri

doi:10.1109/tcsi.2016.2613938

Cited by 21 publications

(7 citation statements)

References 34 publications

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“…To mitigate this, a partial dynamic element matching technique is employed. The results show a THD below −40 dB at 20 MHz [4].…”

Section: Introductionmentioning

confidence: 87%

“…Thus, the focus of the work in [1]- [4] is on the effect of mismatch on scalar weights for frequencies below 100 MHz, while the calibration of timing errors for signal generators operating at higher frequencies is discussed in [5], [10]. In [5], a binary weighted capacitor bank is used in each signal path and an external calibration loop is considered.…”

Section: A Timing Inaccuracies In High Frequencymentioning

confidence: 99%

“…Grenoble Alpes time-shifted signals are generated using digital circuits, and scaling is done using a Digital-to-Analog Converter (DAC). [3], [4] use a digital counter that generates the time-shifted signals while scaling and addition are done using a current steering DAC. However, the mismatch from DAC can degrade the linearity of the output signal.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A harmonic cancellation-based high-frequency on-chip sinusoidal signal generator with calibration using a coarse-fine delay cell

Mamgain

Mir

Tripathi

et al. 2023

2023 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…To mitigate this, a partial dynamic element matching technique is employed. The results show a THD below −40 dB at 20 MHz [4].…”

Section: Introductionmentioning

confidence: 87%

Section: A Timing Inaccuracies In High Frequencymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A harmonic cancellation-based high-frequency on-chip sinusoidal signal generator with calibration using a coarse-fine delay cell

Mamgain

Mir

Tripathi

et al. 2023

2023 IEEE International Symposium on Circuits and Systems (ISCAS)

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show abstract

“…The core operation of DEM is carried out by the scrambler, which executes the process of randomly mapping the inputs to the outputs. The mapping of the scrambler can be considered as a combinations problem [18]. Compared with the full randomization DEM, which suffers from excessive hardware overhead, the partial randomization DEM (PRDEM) technique only utilizes a subset of all combinations and allows for a limited degree of scrambling, providing a trade-off between harmonic distortion suppression and hardware complexity [19,20].…”

Section: Partial Randomization Dynamic Element Matching Based On Switmentioning

confidence: 99%

A 3GS/s 12-bit Current-Steering Digital-to-Analog Converter (DAC) in 55 nm CMOS Technology

Wang¹,

Guo²,

Zhou³

et al. 2019

Electronics

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A 3GS/s 12-bit current-steering digital-to-analog converter (DAC) fabricated in 55 nm complementary metal–oxide–semiconductor (CMOS) technology has been presented. A partial randomization dynamic element matching (PRDEM) method based on switching sequence optimization is proposed to mitigate the mismatch effect and suppress the harmonic distortion with low hardware complexity. In the switching current cell, the cascode structure together with “always-ON” small current sources are used to keep the output impedance high and uniform. A compact layout of the switching current array is carefully designed, featuring short wires routing and small parasitic capacitance. According to the measured results at 3GS/s, this DAC demonstrates a spurious-free dynamic range (SFDR) of 74.64 dBc at low frequency and 50 dBc at 1.5 GHz output. The chip occupies an active area of 0.2 × 0.48 mm2 and consumes a total power of 495 mW.

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“…On the other hand, the works in [3]- [7], [9] present digital-intensive implementations, in which the time-shifted signals are generated using digital circuitry, while they are scaled and combined with the help of a Digital-to-Analog Converter (DAC). Thus, the work in [3], [4] employs a digital counter for generating the time-shifted signals while scaling and addition rely on a current steering DAC. Mismatch issues in the DAC, which would limit the linearity of the generator, are mitigated using a partial dynamic element matching technique.…”

Section: Introductionmentioning

confidence: 99%

On-chip calibration for high-speed harmonic cancellation-based sinusoidal signal generators

Mamgain

Mir

Tripathi

et al. 2022

2022 IEEE 31st Asian Test Symposium (ATS)

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Harmonic cancellation techniques have been exploited for the on-chip generation of high-linearity sinusoidal test stimuli. The sinusoidal signal is generated by combining timeshifted and scaled versions of a periodical signal, in such a way that by properly choosing the time-shifts and weights, the lower order harmonics are canceled. However, process variations and mismatch can degrade the effectiveness of the harmonic cancellation, since precise time-shifts and scale ratios are required. In this regard, timing inaccuracies are especially harmful in the implementation of high-speed harmonic cancelling generators. In this paper, we propose an on-chip calibration architecture that can correct the phase-shift and duty-cycle of the signals with the help of a negative feedback loop. Electrical simulation results at transistor level show the feasibility of the calibration technique for a sinusoidal signal generator implemented in ST 28 nm FD-SOI technology. Obtained results show a Total Harmonic Distortion (THD) better than −60 dB after calibration in an output frequency range from 200 MHz to 4 GHz.

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Partial Dynamic Element Matching Technique for Digital-to-Analog Converters Used for Digital Harmonic-Cancelling Sine-Wave Synthesis

Cited by 21 publications

References 34 publications

A harmonic cancellation-based high-frequency on-chip sinusoidal signal generator with calibration using a coarse-fine delay cell

A harmonic cancellation-based high-frequency on-chip sinusoidal signal generator with calibration using a coarse-fine delay cell

A 3GS/s 12-bit Current-Steering Digital-to-Analog Converter (DAC) in 55 nm CMOS Technology

On-chip calibration for high-speed harmonic cancellation-based sinusoidal signal generators

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