Partly Parallel Overlapped Sum-Product Decoder Architectures for Quasi-Cyclic LDPC Codes

Chen, Ning; Dai, Yongmei; Yan, Zhiyuan

doi:10.1109/sips.2006.352585

Cited by 9 publications

(17 citation statements)

References 12 publications

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“…The results of [75], [48] and [76] all sit above the trend line, despite employing a large number of bits per LLR, as well as a moderate PCM size. This may be partially attributed to their implementation of quasi-cyclic LDPC codes, using partially-parallel architectures, leading to a very efficient use of hardware resources.…”

Section: B Relationships Between Parameters and Each Characteristicmentioning

confidence: 84%

“…The fact that the MSA can facilitate a higher processing throughput than more complicated alternatives such as the SPA [24] is also demonstrated by comparing the results of [75] and [76], which present two very similar designs that vary in algorithm. The design in [76] suffers from a 4-5 Mbps processing throughput drop compared to [75], caused by its employment of the SPA instead of the MSA, as well as by using a non-uniform quantisation scheme for the LLRs.…”

Section: B Relationships Between Parameters and Each Characteristicmentioning

confidence: 98%

“…However, in some cases (eg. [76]) we have derived the clock frequency from other data, as indicated by an asterisk in Table II. Many decoder architectures are highly optimised to the specific characteristics of the single LDPC PCM that they are designed to support (eg. [43], [62], [74]).…”

Section: A Parametersmentioning

confidence: 99%

“…Conversely, the dark points in the top-left represent the fully parallel decoders of [67] and [68], which achieve a very high processing throughput by using few bits, few iterations, a large degree of parallelism and operate on the basis of the MSA [25]. The fact that the MSA can facilitate a higher processing throughput than more complicated alternatives such as the SPA [24] is also demonstrated by comparing the results of [75] and [76], which present two very similar designs that vary in algorithm. The design in [76] suffers from a 4-5 Mbps processing throughput drop compared to [75], caused by its employment of the SPA instead of the MSA, as well as by using a non-uniform quantisation scheme for the LLRs.…”

Section: B Relationships Between Parameters and Each Characteristicmentioning

confidence: 99%

“…In these cases the total processing throughput and resource requirement could be divided by the number of decoders, in order to produce results that correspond to the processing latency of an equivalent design that only considers one frame at a time. However, other designs, such as [42], process multiple frames by making use of spare time within the decoding schedule, with the result that the hardware cost does Number of bits per LLR [76] [48] [75] [47] [61] [77]…”

Section: B Relationships Between Parameters and Each Characteristicmentioning

confidence: 99%

See 4 more Smart Citations

A Survey of FPGA-Based LDPC Decoders

Hailes

Maunder

et al. 2016

IEEE Commun. Surv. Tutorials

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Abstract-Low-Density Parity Check (LDPC) error correction decoders have become popular in communications systems, as a benefit of their strong error correction performance and their suitability to parallel hardware implementation. A great deal of research effort has been invested into LDPC decoder designs that exploit the flexibility, the high processing speed and the parallelism of Field-Programmable Gate Array (FPGA) devices. FPGAs are ideal for design prototyping and for the manufacturing of small-production-run devices, where their insystem programmability makes them far more cost-effective than Application-Specific Integrated Circuits (ASICs). However, the FPGA-based LDPC decoder designs published in the open literature vary greatly in terms of design choices and performance criteria, making them a challenge to compare. This paper explores the key factors involved in FPGA-based LDPC decoder design and presents an extensive review of the current literature. In-depth comparisons are drawn amongst 140 published designs (both academic and industrial) and the associated performance trade-offs are characterised, discussed and illustrated. Seven key performance characteristics are described, namely their processing throughput, processing latency, hardware resource requirements, error correction capability, processing energy efficiency, bandwidth efficiency and flexibility. We offer recommendations that will facilitate fairer comparisons of future designs, as well as opportunities for improving the design of FPGA-based LDPC decoders.

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Section: B Relationships Between Parameters and Each Characteristicmentioning

confidence: 84%

Section: B Relationships Between Parameters and Each Characteristicmentioning

confidence: 98%

Section: A Parametersmentioning

confidence: 99%

Section: B Relationships Between Parameters and Each Characteristicmentioning

confidence: 99%

Section: B Relationships Between Parameters and Each Characteristicmentioning

confidence: 99%

See 3 more Smart Citations

A Survey of FPGA-Based LDPC Decoders

Hailes

Maunder

et al. 2016

IEEE Commun. Surv. Tutorials

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A fully-overlapped multi-mode QC-LDPC decoder architecture for mobile WiMAX applications

Xiang

Bao

Huang

et al. 2010

ASAP 2010 - 21st IEEE International Conference on Application-Specific Systems, Architectures and Processors

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Poster: FPGA based implementation of overlapped QC-LDPC decoder with limited resources

Dijia

Bie

Zheng

et al. 2014

9th International Conference on Communications and Networking in China

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Partly Parallel Overlapped Sum-Product Decoder Architectures for Quasi-Cyclic LDPC Codes

Cited by 9 publications

References 12 publications

A Survey of FPGA-Based LDPC Decoders

A Survey of FPGA-Based LDPC Decoders

A fully-overlapped multi-mode QC-LDPC decoder architecture for mobile WiMAX applications

Poster: FPGA based implementation of overlapped QC-LDPC decoder with limited resources

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