A fully-overlapped multi-mode QC-LDPC decoder architecture for mobile WiMAX applications

Xiang, Bo; Bao, Dan; Huang, Shuangqu; Zeng, Xiaoyang

doi:10.1109/asap.2010.5540958

Cited by 5 publications

(4 citation statements)

References 17 publications

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“…In this section, we quantify the flexibility of each channel decoder by the number of supported combinations of block length K and coding rate R. Figure 11 characterises the flexibility, scaled average area-efficiency and energy-efficiency that is achieved by each turbo, LDPC and polar decoder ASIC considered. In the case of the turbo decoders, the number of information block lengths K supported is determined by the number of interleavers supported, which is 188 Average Scaled Energy Efficiency (bit/nJ) [45], [58], [63], [67]- [72] [65], [73]- [76] [52], [77], [78] [64], [79], [80] [51], [81]- [85] Inflexible Fl ex ib le Fig. 11: Area-efficiency (M bps/mm 2 ) versus the reconfiguration flexibility between state-of-the-art turbo, LDPC and inflexible polar decoder ASICs when scaled to 65 nm.…”

Section: Reconfiguration Flexibility Vs Area-and Energyefficiencymentioning

confidence: 99%

Survey of Turbo, LDPC, and Polar Decoder ASIC Implementations

Shao

Hailes

Wang

et al. 2019

IEEE Commun. Surv. Tutorials

116

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Channel coding may be viewed as the bestinformed and most potent component of cellular communication systems, which is used for correcting the transmission errors inflicted by noise, interference and fading. The powerful turbo code was selected to provide channel coding for Mobile Broad Band (MBB) data in the 3G UMTS and 4G LTE cellular systems. However, the 3GPP standardization group has recently debated whether it should be replaced by Low Density Parity Check (LDPC) or polar codes in 5G New Radio (NR), ultimately reaching the decision to adopt the LDPC code family for enhanced Mobile Broad Band (eMBB) data and polar codes for eMBB control. This paper summarises the factors that influenced this debate, with a particular focus on the Application Specific Integrated Circuit (ASIC) implementation of the decoders of these three codes. We show that the overall implementation complexity of turbo, LDPC and polar decoders depends on numerous other factors beyond their computational complexity. More specifically, we compare the throughput, error correction capability, flexibility, area efficiency and energy efficiency of ASIC implementations drawn from 110 papers and use the results for characterising the advantages and disadvantages of these three codes as well as for avoiding pitfalls and for providing design guidelines.

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Section: Reconfiguration Flexibility Vs Area-and Energyefficiencymentioning

confidence: 99%

Survey of Turbo, LDPC, and Polar Decoder ASIC Implementations

Shao

Hailes

Wang

et al. 2019

IEEE Commun. Surv. Tutorials

116

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“…In addition, due to random location of nonzero submatrices and correlations between consecutive block rows of H BASE , extrinsic information exchange can lead to memory access conflicts. These limitations were addressed by Xiang et al in [34], whereby the authors presented an overlapped TDMP decoding algorithm. The design proposes a block row and column permutation criterion in order to reduce correlation between consecutive rows and uniform distribution of zero and nonzero matrices in columns, with a smart memory management technique.…”

Section: Designmentioning

confidence: 99%

“…Explicitly enabling the decoding of just 20 codes, however, lowers its FE measure. Among serial PE-based run time flexible solutions discussed above, the work in [34] achieves very high throughput, TAR and DE with a small area occupation of 2.46 mm 2 , yielding the best FE of all decoders. A full-mode reconfigurable solution based on parallel check node in [35] 10 VLSI Design Among the ASIP solutions (Table 5), the work in [40] cannot effectively be compared to the others in terms of area, not providing complete estimations.…”

Section: Designmentioning

confidence: 99%

Flexible LDPC Decoder Architectures

Awais

Condo

2012

VLSI Design

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Flexible channel decoding is getting significance with the increase in number of wireless standards and modes within a standard. A flexible channel decoder is a solution providing interstandard and intrastandard support without change in hardware. However, the design of efficient implementation of flexible low-density parity-check (LDPC) code decoders satisfying area, speed, and power constraints is a challenging task and still requires considerable research effort. This paper provides an overview of state-of-the-art in the design of flexible LDPC decoders. The published solutions are evaluated at two levels of architectural design: the processing element (PE) and the interconnection structure. A qualitative and quantitative analysis of different design choices is carried out, and comparison is provided in terms of achieved flexibility, throughput, decoding efficiency, and area (power) consumption.

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“…Although the algorithms and approximation techniques are quite similar, the proposed architectures show much variety in each implementation. ASIC implementations [3,4,5,6,7,8,9] mainly focus on squeezing highly parallelized decoders into smaller silicon areas, whereas FPGA implementations [10,11,12,13,14,15,16,17] focus on efficient utilization of the inherent resources. Therefore, the challenge of optimizing large permutation networks in ASIC designs has mostly turned into designing dynamic RAM-based networks in FPGA designs.…”

Section: Introductionmentioning

confidence: 99%

Dual port ram based layered decoding for Multi Rate Quasi-Cyclic LDPC codes

Yesil

Arslan

2014

2014 12th International Conference on Signal Processing (ICSP)

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This paper presents a generic RAM based FPGA architecture for decoding of Multi Rate Quasi-Cycling LDPC codes. RAM based decoding enables us to reduce permutation networks into simple address controllers. Moreover, utilizing Block RAMs with various aspect ratios in an FPGA provides flexibility ranging from area driven compact designs to fully parallelized high throughput designs. Utilizing the read-first property of the RAMs, the proposed design efficiently exploits the dual port Block RAM resources by accessing all the four ports at the same time. Such facilities of recent FPGA devices have been combined with the well known layered decoding algorithm with non-linearly mapped Min-Sum approximation in order to obtain area efficient yet high throughput decoders. The proposed decoder architecture has been verified on Xilinx XC7Z020 FPGA device for IEEE 802.16e Wimax LDPC codes. 340Mbps of information throughput has been observed at an operating frequency of 150MHz.

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A fully-overlapped multi-mode QC-LDPC decoder architecture for mobile WiMAX applications

Cited by 5 publications

References 17 publications

Survey of Turbo, LDPC, and Polar Decoder ASIC Implementations

Survey of Turbo, LDPC, and Polar Decoder ASIC Implementations

Flexible LDPC Decoder Architectures

Dual port ram based layered decoding for Multi Rate Quasi-Cyclic LDPC codes

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