Pass-transistor adiabatic logic withNMOS pull-down configuration

Liu, F.; Lau, K.T.

doi:10.1049/el:19980571

Cited by 65 publications

(25 citation statements)

References 3 publications

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“…Among others we take into consideration the ECRL (E cient Charge Recovery Logic) (Moon and Jeong 1996), IECRL (Improved ECRL) (Liu and Lau 1998b), PAL (Pass transistor Adiabatic Logic) (Oklobdẑ zija et al 1997) and PFAL (Positive Feedback Adiabatic Logic) (Vetuli et al 1996) logic families. These exhibit many similarities in circuit topology and in theory of operation and can therefore easily be compared.…”

Section: Flip-flop Style Adiabatic Logic Circuitsmentioning

confidence: 99%

A comparison of some circuit schemes for semi-reversible adiabatic logic

Blotti¹,

Pascoli²,

Saletti³

2002

International Journal of Electronics

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Four flip-flop-like adiabatic logic circuits, suited for a standard cell library implementation, were compared in terms of absolute energy consumption and effectiveness of adiabatic energy recovery. The energy performance of ECRL, IECRL, PAL and PFAL logic circuits was determined, by means of SPICE simulation, as a function of capacitive load and operational frequency. The comparison showed that the PFAL circuit is the best flip-flop-based adiabatic solution as far as power consumption is concerned

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Section: Flip-flop Style Adiabatic Logic Circuitsmentioning

confidence: 99%

A comparison of some circuit schemes for semi-reversible adiabatic logic

Blotti¹,

Pascoli²,

Saletti³

2002

International Journal of Electronics

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“…However, there is no adiabatic circuit design which can cover all requirements. Most current designs have a dynamic structure [5] such as the energy efficient logic (EEL) [6], the adiabatic differential cascade voltage switch with complementary pass-transistor logic (ADCPL) [7] and others [8][9][10][11][12][13][14]. The high efficient energy recovery logic [15] has an additional block for the effective recovery path.…”

Section: Introductionmentioning

confidence: 99%

The Combinational and Sequential Adiabatic Circuit Design and Its Applications

Wisetphanichkij

Dejhan

2009

Circuits Syst Signal Process

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In this paper, a new design of adiabatic circuit, called the quasi-static efficient charge recovery logic (QSECRL) is proposed. To achieve minimum energy consumption, this paper proposes a technique to reduce channel resistance and remove diodes from the signal path. This design method can be implemented in both combination logic and sequential logic. The counter circuit and the 8-bit carry look-ahead (CLA) circuit, a more complex circuit, are selected to evaluate this proposed design. All simulations in this paper have been implemented by SPICE with the 0.8 µm MO-SIS technology MOS transistor model under 2-volt (peak-peak) sinusoidal powerclock supply. The results show significantly improved performance of the 8-bit CLA circuit with 20-30 fJ and 70 fJ energy consumption at 10-100 MHz and 500 MHz operating frequency, respectively.Keywords Adiabatic circuit · Low-voltage low-power circuit · Digital circuit List of SymbolsV d Voltage drop in diode V φ Peak-peak voltage of power-clock supply (φ) V CL Voltage drop in capacitive load V th MOS transistor threshold voltage R ch MOS transistor channel resistance C L Capacitive load T Period of power-clock supply

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“…In recent years, several adiabatic logic families have been proposed for low power systems [2][3][4][5]. Some adiabatic logic circuits, such as the efficient charge recovery logic (ECRL) [6] and the pass-transistor adiabatic logic circuits with NMOS pull-down configuration (PAL-2N) [7] etc, are applied for memories, and they are used to drive address lines, bit lines, and word lines.…”

Section: Introductionmentioning

confidence: 99%

Low-Power Register File Using N-type and P-type Adiabatic Logic Circuits

2009

2009 Pacific-Asia Conference on Circuits, Communications and Systems

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A 32×32 register file based on dual transmission gate adiabatic logic (DTGAL) is implemented with TSMC 0.18μm process. The energy of all nodes with large capacitances including storage cells can be well recovered without non-adiabatic loss. Full-custom layouts are drawn. The energy and functional simulations have been performed using the net-list extracted from their layouts. The results show the adiabatic register file can work very well.

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Pass-transistor adiabatic logic withNMOS pull-down configuration

Cited by 65 publications

References 3 publications

A comparison of some circuit schemes for semi-reversible adiabatic logic

A comparison of some circuit schemes for semi-reversible adiabatic logic

The Combinational and Sequential Adiabatic Circuit Design and Its Applications

Low-Power Register File Using N-type and P-type Adiabatic Logic Circuits

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