The Combinational and Sequential Adiabatic Circuit Design and Its Applications

Abstract

In this paper, a new design of adiabatic circuit, called the quasi-static efficient charge recovery logic (QSECRL) is proposed. To achieve minimum energy consumption, this paper proposes a technique to reduce channel resistance and remove diodes from the signal path. This design method can be implemented in both combination logic and sequential logic. The counter circuit and the 8-bit carry look-ahead (CLA) circuit, a more complex circuit, are selected to evaluate this proposed design. All simulations in this paper have been implemented by SPICE with the 0.8 µm MO-SIS technology MOS transistor model under 2-volt (peak-peak) sinusoidal powerclock supply. The results show significantly improved performance of the 8-bit CLA circuit with 20-30 fJ and 70 fJ energy consumption at 10-100 MHz and 500 MHz operating frequency, respectively.Keywords Adiabatic circuit · Low-voltage low-power circuit · Digital circuit List of SymbolsV d Voltage drop in diode V φ Peak-peak voltage of power-clock supply (φ) V CL Voltage drop in capacitive load V th MOS transistor threshold voltage R ch MOS transistor channel resistance C L Capacitive load T Period of power-clock supply

Low-Power Adiabatic Computing with Modified Quasi Static Energy Recovery Logic of MQSERL 4x4 multiplier

“…With the developing prerequisite of convenient correspondence many research have been done to lessen vitality scattering [1]- [4], among them adiabatic rationale procedure [5] is extremely encouraging. In adiabatic circuits vitality scattering happens because of adiabatic and non-adiabatic misfortunes.…”

“…Be that as it may, because of the additional MOSFET diodes in charging and releasing way somewhat bigger power dissemination than QSERL circuits happen. Because of these difficulties with detailed adiabatic rationale circuits [11][12][13][14][15][16][17][18][19] we propose altered semi static vitality recuperation rationale (MQSERL) circuit. MQSERL acquires every one of the upsides of as of late detailed QSERL circuits with extra enhancement in power sparing by decreasing the non-adiabatic misfortunes just as adiabatic misfortunes.…”

Design of Low Power Carry Look-Ahead Adder Using Single Phase Clocked Quasi-Static Adiabatic Logic

“…The last two losses are associated with fully adiabatic circuits, whereas non-adiabatic losses are related to quasi/semi-adiabatic circuits [10,11]. Leakage losses are proportional to the clock period and are negligible in comparison to the other two and depend on current or voltage drawn from the source, load capacitance, charging path resistance, and transition time [12,13]. Non-adiabatic losses can be eliminated using reversible logic.…”

Performance Analysis of Modified QSERL Circuit

“…Due to these challenges with reported adiabatic logic circuits [11][12][13][14][15][16][17][18][19] we propose modified quasi static energy recovery logic (MQSERL) circuit. MQSERL inherits all the advantages of recently reported QSERL circuits with additional improvement in power saving by reducing the non adiabatic losses as well as adiabatic losses.…”