Patching Processor Design Errors with Programmable Hardware

Sarangi, Smruti R.; Narayanasamy, Satish; Carneal, B.; Tiwari, Abhishek; Calder, Brad; Torrellas, Josep

doi:10.1109/mm.2007.19

Cited by 46 publications

(34 citation statements)

References 7 publications

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“…A related work by Sarangi et al [24], which appeared after the initial publication of our solution in [27], suggests a similar mechanism for hardware patching. An error in this work is identified by its fingerprint: a set of conditions and a time interval during which these conditions are satisfied when the error occurs.…”

Section: B Related In-field Repair Solutionssupporting

confidence: 57%

“…Similar to our work, this mechanism relies on internal signals being observed by the programmable errorchecking module. However, the matcher in [24] is distributed and contains multiple modules that detect the occurrence of various events and identify if they correspond to an error. The work also proposes several recovery mechanisms, including dynamic microcode editing, checkpointing, and hypervisor support.…”

Section: B Related In-field Repair Solutionsmentioning

confidence: 99%

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Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors

Wagner

Bertacco

Austin

2008

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Functional correctness is a vital attribute of any hardware design. Unfortunately, due to extremely complex architectures, widespread components, such as microprocessors, are often released with latent bugs. The inability of modern verification tools to handle the fast growth of design complexity exacerbates the problem even further. In this paper, we propose a novel hardware-patching mechanism, called the field-repairable control logic (FRCL), that is designed for in-the-field correction of errors in the design's control logic-the most common type of defects, as our analysis demonstrates. Our solution introduces an additional component in the processor's hardware, a state matcher, that can be programmed to identify erroneous configurations using signals in the critical control state of the processor. Once a flawed configuration is "matched," the processor switches into a degraded mode, a mode of operation which excludes most features of the system and is simple enough to be formally verified, yet still capable to execute the full instruction-set architecture at one instruction at a time. Once the program segment exposing the design flaw has been executed in a degraded mode, we can switch the processor back to its full-performance mode. In this paper, we analyze a range of approaches to selecting signals comprising the processor's critical control state and evaluate their effectiveness in representing a variety of design errors. We also introduce a new metric (average specificity per signal) that encodes the bug-detection capability and amount of control state of a particular critical signal set. We demonstrate that the FRCL can support the detection and correction of multiple design errors with a performance impact of less than 5% as long as the incidence of the flawed configurations is below 1% of dynamic instructions. In addition, the area impact of our solution is less than 2% for the two microprocessor designs that we investigated in our experiments.

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Section: B Related In-field Repair Solutionssupporting

confidence: 57%

Section: B Related In-field Repair Solutionsmentioning

confidence: 99%

Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors

Wagner

Bertacco

Austin

2008

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…AAM instructions in the last five fetches will be tracked. Design bug detection using programmable hardware is given by Sarangi et al (2007). In Sarangi et al (2007), sources of design errors are identified as given below:…”

Section: Fault Recoverymentioning

confidence: 99%

“…In Sarangi et al (2007), after the programmable hardware detects faults, applying recovery using one of the following four techniques were discussed.…”

Section: Fault Recoverymentioning

confidence: 99%

On the field design bug tolerance on a multi-core processor using FPGA

Sriraman

Pattabiraman

2017

IJHPCN

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Abstract:In recent times, with increased transistor density, it is impossible to verify all the components exhaustively for different scenarios. This results in design bugs also known as extrinsic hardware faults to escape into the processor chip in spite of various levels of testing. Hence, handling design bugs efficiently on the field is a necessity in modern multi-core processors. In this paper, an architecture and algorithm for self-repairing of design bugs in the data path using FPGA is proposed. The FPGA is re-configured during the run-time to take over the functions of the faulty component. To verify the effectiveness of the proposed design a representative sample of five faults are injected and handled. The proposed design's area overhead and time overhead calculations are done using Cadence ncverilog and gem5 simulator respectively. The area overhead of the proposed design is < 1% and performance improvement is around 2.5% compared to the existing techniques.

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“…In fact, manufacturing defect levels are expected to increase sharply in future technologies [2], further decreasing yield. In order to combat these trends, adding space redundancy and using reconfigurability have been proposed in different contexts to reduce the number of silicon respins [3], [4]. Double and Triple Modular Redundancy (DMR and TMR) are examples of design techniques that replicate parts of a design with the aim of yield enhancement as well as chip reliability improvement.…”

Section: Introductionmentioning

confidence: 99%

On error tolerance and Engineering Change with Partially Programmable Circuits

Mangassarian

Yoshida

Veneris

et al. 2012

17th Asia and South Pacific Design Automation Conference

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Abstract-The growing size, density and complexity of modern VLSI chips are contributing to an increase in hardware faults and design errors in the silicon, decreasing manufacturing yield and increasing the design cycle. The use of Partially Programmable Circuits (PPCs) has been recently proposed for yield enhancement with very small overhead. This new circuit structure is obtained from conventional logic by replacing some subcircuits with programmable LUTs. The present paper lays the theoretical groundwork for evaluating PPCs with Quantified Boolean Formula (QBF) satisfiability. First, QBF models are constructed to calculate the fault tolerance and design error tolerance of a PPC, namely the percentages of faults and design errors that can be masked using LUT reconfigurations. Next, zero-cost Engineering Change Order (ECO) in PPCs is investigated. QBF formulations are given for performing ECOs, and for quantifying the ECO coverage of a PPC architecture. Experimental results are presented evaluating PPCs from [1], demonstrating the applicability and accuracy of the proposed formulations.

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Patching Processor Design Errors with Programmable Hardware

Cited by 46 publications

References 7 publications

Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors

Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors

On the field design bug tolerance on a multi-core processor using FPGA

On error tolerance and Engineering Change with Partially Programmable Circuits

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