Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors

Abstract

Abstract-Functional correctness is a vital attribute of any hardware design. Unfortunately, due to extremely complex architectures, widespread components, such as microprocessors, are often released with latent bugs. The inability of modern verification tools to handle the fast growth of design complexity exacerbates the problem even further. In this paper, we propose a novel hardware-patching mechanism, called the field-repairable control logic (FRCL), that is designed for in-the-field correction of errors in the design's control logic-the most common type of defects, as our analysis demonstrates. Our solution introduces an additional component in the processor's hardware, a state matcher, that can be programmed to identify erroneous configurations using signals in the critical control state of the processor. Once a flawed configuration is "matched," the processor switches into a degraded mode, a mode of operation which excludes most features of the system and is simple enough to be formally verified, yet still capable to execute the full instruction-set architecture at one instruction at a time. Once the program segment exposing the design flaw has been executed in a degraded mode, we can switch the processor back to its full-performance mode. In this paper, we analyze a range of approaches to selecting signals comprising the processor's critical control state and evaluate their effectiveness in representing a variety of design errors. We also introduce a new metric (average specificity per signal) that encodes the bug-detection capability and amount of control state of a particular critical signal set. We demonstrate that the FRCL can support the detection and correction of multiple design errors with a performance impact of less than 5% as long as the incidence of the flawed configurations is below 1% of dynamic instructions. In addition, the area impact of our solution is less than 2% for the two microprocessor designs that we investigated in our experiments.

Online design bug detection: RTL analysis, flexible mechanisms, and evaluation

“…More recently, Sarangi et al [20] analyzed the design bugs in ten modern commercial microprocessors from Intel, AMD, IBM and Motorola, and Narayanasamy et al [17] analyzed the design bugs in two microprocessors: Intel's Pentium 4 and AMD's Athlon 64. Another study by Wagner et al [26] analyzed the design bugs in Intel StrongARM SA1100 and IBM PowerPC 750GX. The analysis in all of these studies was based on information extracted from the available microprocessor errata sheets e.g.…”

“…Further action is required to avert the design bug and avoid corrupting the execution. This is commonly achieved through recovery support where the system state recovers to the last validated/correct state [18,21] and execution is guided from there in a way that the design bug is averted [19,26,17].…”

“…By rolling back the system state to the last validated and correct system state, execution can be guided by design bug avoidance techniques in a way to avert the design bug. Several design bug avoidance techniques have already been proposed in the research literature [19,26,17]. Any further advancement toward this direction is left for future work.…”

“…Online Design Bug Detection: Recently, studies have brought to attention the increasing rate of discovered design bugs in modern processors [20,17,26]. These works suggest employing in-the-field design bug detection and recovery as an approach to mitigate the negative Table 4.…”

Caspar: Hardware patching for multicore processors

“…To cope with this challenge and prevent costly re-spins, researchers have proposed several runtime validation systems, which can be divided into two groups: checker-based [3,9,10] and patching [12,15] solutions. In the former, the detection is done by a special checker block, which dynamically analyzes the execution trace and detects anomalies or violations of invariants at runtime.…”