Path hashing to accelerate delay fault simulation

Abstract

This paper presents an ecient approach to path delay fault simulation. We accelerate fault simulation by more than one order of magnitude with a new speed u p t e chnique called path hashing. An intelligent path identication method allows to deal with circuits containing two orders of magnitude more p aths than state-of-the-art tools. Using these techniques larger circuits can be handled with a reasonable amount of time and memory.

Bit parallel test pattern generation for path delay faults

“…A lot of research has been devoted to the topic of path delay fault testing. Best suited algorithms for fault simulation [1,2,3,4] have been proposed. All state-ofthe-art tools use bit-parallelity for fault simulation.…”