Various satisfiability problems in combinational logic

lhis paper analyzes fault dependency in sequential circuits to accelerate parallel automatic test pattern generation (ATPG). We present the new algorithms improved fault collapsing and fault m g i n g j b r an @cient f d t ordering to speedup ATPG. Experimental results obtained for sequential and fault parallel ATPG show the ejfciency of the proposed methods.

This paper presents an ecient approach to path delay fault simulation. We accelerate fault simulation by more than one order of magnitude with a new speed u p t e chnique called path hashing. An intelligent path identication method allows to deal with circuits containing two orders of magnitude more p aths than state-of-the-art tools. Using these techniques larger circuits can be handled with a reasonable amount of time and memory.