A single-path-oriented fault-effect propagation in digital circuits considering multiple-path sensitization

Henftling, M.; Wittmann, H.C.; Antreich, K.J.

doi:10.1109/iccad.1995.480027

Cited by 16 publications

(20 citation statements)

References 20 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…The work in [5] on Single-Path-Oriented Fault Effect Propagation (SPOP) has indicated potential runtime savings by avoiding the justification procedure. This idea can complement our approach and yield further runtime gains.…”

Section: Runtime Bottlenecks In Rr Frameworkmentioning

confidence: 99%

“…Justifying the values used to propagate the fault then requires finding satisfying primary input values. The works in [5,11] explore different combinations of decision strategies to achieve good RR runtime.…”

Section: Rr Frameworkmentioning

confidence: 99%

“…However, we have observed that this complementary approach identifies fewer redundancies, which leads to unacceptable area and timing degradation for the limited runtime improvement. The algorithms in [11] expand on [5] by using static learning techniques and decision heuristics to potentially identify redundancies more efficiently.…”

Section: Runtime Bottlenecks In Rr Frameworkmentioning

confidence: 99%

“…RR algorithms are traditionally based on ATPG search algorithms [7], which derive a sensitizing input pattern, if one exists, for each pin in the design. Continual advances in ATPG algorithms [5,7,11,12] have led to significant runtime improvements allowing most practical circuit designs to be analyzed in polynomial time. Additional innovation in satisfiability solving in both clause learning [10] and fast implications procedure [8] further improves RR algorithms [12].…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Multi-mode redundancy removal

Plaza

Saxena

Shiple

et al. 2011

2011 12th International Symposium on Quality Electronic Design

View full text Add to dashboard Cite

Redundancy removal, i.e., identifying and eliminating redundant logic, is an essential optimization strategy for decreasing design area, reducing critical path delay, and simplifying circuit testability analysis.However, redundancy removal strategies invoke time-consuming proof engines with worst-case exponential behavior. While continual enhancements to heuristics resident in these engines result in large average runtime improvements, inherent intractability still leads to sub-optimal optimization and occasional large runtime outliers. Such outliers are unacceptable in an industrial setting where an outlier compromises design turnaround time. Our work introduces a semi-local optimization algorithm that mitigates the inherent intractability in redundancy removal and eliminates crippling runtime outliers. We further embed this algorithm within a framework that minimizes any negative impact to delay and area metrics. Using the cutting-edge Synopsys® Design Compiler® logic synthesis tool, we demonstrate 1) statistical neutrality in area and timing while achieving consistent runtime improvements on a large set of proprietary circuit designs of varying type and complexity and 2) over 50% runtime improvement on a suite of computationally intractable industrial designs, even when measured at the end of the physical synthesis flow.

show abstract

Section: Runtime Bottlenecks In Rr Frameworkmentioning

confidence: 99%

Section: Rr Frameworkmentioning

confidence: 99%

Section: Runtime Bottlenecks In Rr Frameworkmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Multi-mode redundancy removal

Plaza

Saxena

Shiple

et al. 2011

2011 12th International Symposium on Quality Electronic Design

View full text Add to dashboard Cite

show abstract

“…Fault propagation is widely carried out for digital circuits, but not yet exhaustively tested for analog circuits [6], [7]. Difficulty stems from the fact that when the faulty behavior propagates from faulty block to non-faulty block of circuit, it may force the non-faulty block into highly nonlinear regions of operation.…”

Section: Introductionmentioning

confidence: 99%

High level fault modeling and fault propagation in analog circuits using NLARX automated model generation technique

Farooq

Xia

Hussin

et al. 2012

2012 4th International Conference on Intelligent and Advanced Systems (ICIAS2012)

View full text Add to dashboard Cite

It is known that fault modeling and fault propagation in analog circuits are extremely important and more challenging than in digital circuits. Several automated model generation (AMG) techniques are developed to model the nonlinear behavior of faulty analog circuits. However, most of the modeling techniques are performed under the MATLAB environment which is impractical and the models cannot be utilized in electronic circuits. To perform high level fault modeling (HLFM) and fault propagation (FP) on system level, the models need to be translated into hardware description language (HDL) models such as VHDL-AMS or Verilog-AMS models. In this paper, several faults are modeled for transistor level analog circuits using nonlinear autoregressive exogenous (NLARX) AMG technique in MATLAB. The resulting MATLAB models are translated into VHDL-AMS behavioral models. HLFM and FP are successfully implemented for benchmark analog circuits: inverting amplifier and biquadratic low-pass filter circuits.

show abstract