IGRAINE-an Implication GRaph-bAsed engINE for fast implication, justification, and propagation

Tafertshofer, P.; Ganz, Andreas; Antreich, K.J.

doi:10.1109/43.856977

Cited by 42 publications

(22 citation statements)

References 45 publications

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“…In contrast, there also exist approaches based on Boolean satisfiability [24], [31], [26], [32], [17], [11]. Due to the lack of efficient SAT solvers, the early approaches did not become popular.…”

Section: Introductionmentioning

confidence: 99%

Structural heuristics for SAT-based ATPG

Tille

Eggersglüß

et al. 2009

2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC)

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Abstract-Due to ever increasing design sizes more efficient tools for Automatic Test Pattern Generation (ATPG) are needed. The application of the Boolean satisfiability problem (SAT) to ATPG has been shown to be a robust alternative to traditional ATPG techniques. A major challenge of research in the field of SAT-based ATPG is to obtain a robust algorithm which can solve hard SAT instances reliably without slowing down easy-to-solve SAT instances. This is particular important, since easy-to-solve SAT instances form the majority of an ATPG run. This paper proposes two structural heuristics. The first one uses testability measurements to obtain an improved initial variable order, while the second heuristic prunes many easy-to-test faults by finding easy-to-control paths. Experimental results on large industrial designs confirm that the proposed methodologies result in a significant overall speed-up.

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Section: Introductionmentioning

confidence: 99%

Structural heuristics for SAT-based ATPG

Tille

Eggersglüß

et al. 2009

2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC)

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“…Boolean SAT finds applications in many areas of circuit design and verification such as Bounded Model Checking [1], Redundancy Identification, and Equivalence Checking [15]. State-of-the-art SAT algorithms, as implemented in tools such as ZCHAFF [13] , have demonstrated that very hard SAT problems can now be solved in reasonable time.…”

Section: Introductionmentioning

confidence: 99%

“…However, SAT performs much better than ATPG on hard SAT problems, due to conflict-based learning. SAT can do quite well on manufacturing test-pattern generation and logic analysis [15], once it has access to structural information. Solution Size: SAT assigns more primary inputs than ATPG when finding a satisfying pattern.…”

Section: Introductionmentioning

confidence: 99%

SATORI-a fast sequential SAT engine for circuits

Iyer

Parthasarathy

Cheng

2003

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

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We describe the design and implementation of SATORI -a fast sequential justification engine based on state-of-the-art SAT and ATPG techniques. We present several novel techniques that propel SATORI to a demonstrable 10x improvement over a commercial engine. Traditional sequential justification based on ATPG or, on a bounded model of the sequential circuit using SAT, has diverging strengths and weaknesses. In this paper, we contrast these techniques and describe how their strengths are combined in SATORI. We use conflict-based learning in each timeframe and illegal state learning across time-frames. This enables both combinational and sequential back-jumping. We experimentally analyze the main features of SATORI by comparing SATORI's performance against a state-of-the-art SAT solver -ZCHAFF [13] using a bounded model, and a commercial sequential ATPG engine performing justification. Additional results are presented for SATORI versus the commercial ATPG engine and VIS [16] on ISCAS '89 and ITC'99 benchmark circuits for an application to assertion checking.

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“…In contrast, there also exist approaches based on Boolean satisfiability (SAT) [8], [13], [14], [2]. In particular for hard-to-solve problem instances, SAT-based methods proved to be highly advantageous.…”

Section: Introductionmentioning

confidence: 99%

A fast untestability proof for SAT-based ATPG

Tille

Drechsler

2009

2009 12th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems

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Abstract-AutomaticTest Pattern Generation (ATPG) based on Boolean satisfiability (SAT) has been shown to be a beneficial complement to traditional ATPG techniques. Boolean solvers work on instances given in Conjunctive Normal Form (CNF). The required transformation of the ATPG problem into CNF is one main part of SAT-based ATPG and needs a significant portion of the overall run time. Solving the SAT instance is the other main part. Here, the time needed is often negligible -especially for untestable faults This paper presents a preprocessing technique that accelerates the classification of untestable faults. Those occur more frequently with increasing design sizes in industrial practice. In order to avoid overhead on testable faults, an untestability prediction is motivated. This increases the robustness of the entire ATPG process. The efficiency of the proposed method is shown during the experiments.

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IGRAINE-an Implication GRaph-bAsed engINE for fast implication, justification, and propagation

Cited by 42 publications

References 45 publications

Structural heuristics for SAT-based ATPG

Structural heuristics for SAT-based ATPG

SATORI-a fast sequential SAT engine for circuits

A fast untestability proof for SAT-based ATPG

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