SATORI-a fast sequential SAT engine for circuits

Abstract

We describe the design and implementation of SATORI -a fast sequential justification engine based on state-of-the-art SAT and ATPG techniques. We present several novel techniques that propel SATORI to a demonstrable 10x improvement over a commercial engine. Traditional sequential justification based on ATPG or, on a bounded model of the sequential circuit using SAT, has diverging strengths and weaknesses. In this paper, we contrast these techniques and describe how their strengths are combined in SATORI. We use conflict-based learning in each timeframe and illegal state learning across time-frames. This enables both combinational and sequential back-jumping. We experimentally analyze the main features of SATORI by comparing SATORI's performance against a state-of-the-art SAT solver -ZCHAFF [13] using a bounded model, and a commercial sequential ATPG engine performing justification. Additional results are presented for SATORI versus the commercial ATPG engine and VIS [16] on ISCAS '89 and ITC'99 benchmark circuits for an application to assertion checking.

A survey of recent advances in SAT-based formal verification

“…2.2 is one such attempt. Another significant step in this direction has been reported by Iyer et al in the SATORI solver [59]. SATORI is a complete algorithm for sequential Boolean reasoning.…”

“…A slight tuning of these heuristics for the BMC problem [88] can fur-ther enhance the performance. On the other hand, BMC tools using circuit-based SAT solvers (e.g., [41,59,64]) essentially use some variant of the J-frontier justification heuristic popularly used in sequential ATPG tools.…”

“…A desirable solution to this is the development of a sequential reasoning engine that implements all the features of modern SAT solvers but does not require explicit unrolling of the circuit. A first attempt at implicit time frame unrolling has been made in the SATORI solver [59] that partly integrates ideas from modern SAT solvers and sequential ATPG tools.…”

An efficient finite-domain constraint solver for circuits

“…If this is unsatisfiable, then we have to back-track and repeat the process, by learning a conflict clause that avoids the assignments on the interface -a blocking clause [10]. We can use all Boolean values on the interface points as a learned clause in SAT, to drive the solver into the solution space.…”

“…The Boolean solver finds values, which need to be set on IP in order to satisfy the objective. We use 3-valued search combined with a reduction algorithm [10], in the Boolean solver. This reduces the number of assignments on the interface points, which are needed to satisfy the objective.…”