Pattern decomposition and process integration of self-aligned double patterning for 30nm node NAND FLASH process and beyond

Abstract

As IC manufacturing goes from 45nm to 30nm node half-pitch, the lithography process k1 factor will fall below 0.25 by using water-based ArF-immersion scanner. To bridge the gap between ArF-immersion and next generation lithography, which is not ready yet for production, Double Patterning Technology (DPT) has been evaluated and identified as a promising solution as it utilizes existing equipment and processes. Self Aligned Double Patterning (SADP) has the advantage of dense array definition without overlay issue and is hence useful for memory device; but its characteristic restricts the feasibility of two-dimensional circuit pattern definition on the other hand.This paper describes the ideas of 30nm node NAND FLASH cell circuit critical feature (pickup, gate, contact array) definition by decomposing the target patterns to SADP defined dense array in conjunction with cropping and/or periphery masks steps. The concerns and issues of cropping/periphery mask step process integration as well as SADP alignment algorithm are investigated, and the countermeasures with alternative process schemes and novel frame designs are presented. Finally, simulation prediction has shown that the capability of 30nm NAND FLASH critical features patterning with depth of focus equal to or above 0.15um is expected at each mask step by ArF-dry lithography.

Full area pattern decomposition of self-aligned double patterning for 30nm node NAND FLASH process

“…Among various DPT schemes, SADP has the advantage of excellent overlay performance in pitch splitting, and is therefore very useful for manufacturing devices with regular dense patterns, such as FLASH memory devices. Even though the nature of SADP restricts its freedom of 2-D or through-pitch pattern definition, recent studies [2,3] have demonstrated the capability of implementing SADP on both DRAM and logic layouts with the adoption of gridded or non-gridded design rule, as schematically shown in Figs.1 and 2. In SPIE 2009 [3], we had demonstrated the ideas of 30nm node NAND FLASH cell circuit critical feature definition by decomposing the target patterns to SADP defined dense array in conjunction with cropping and/or periphery masks steps, based on manual design.…”

“…Even though the nature of SADP restricts its freedom of 2-D or through-pitch pattern definition, recent studies [2,3] have demonstrated the capability of implementing SADP on both DRAM and logic layouts with the adoption of gridded or non-gridded design rule, as schematically shown in Figs.1 and 2. In SPIE 2009 [3], we had demonstrated the ideas of 30nm node NAND FLASH cell circuit critical feature definition by decomposing the target patterns to SADP defined dense array in conjunction with cropping and/or periphery masks steps, based on manual design. In this paper, we extend the previous works on manual-based decomposition to a more sophisticated use on full-area NAND FLASH critical layer layout decomposition by utilizing an automated electronic design (EDA) tool.…”