Extreme bottom-up copper superfilling of through-silicon-vias (TSV) is demonstrated using a CuSO 4 -H 2 SO 4 electroplating bath containing chloride and a polyether suppressor. Via filling occurs almost exclusively by deposition on the bottom via surface. The differential between the incoming fluxes of hydrated metal cations and larger suppressor molecules is accentuated by the recessed via geometry and accounts for preferential metal deposition initiating and growing from the bottom surface. The bottom-up growth front eventually propagates beyond the via opening and a substantial overburden develops. Feature filling is enhanced in electrolytes with a high [Cu 2+ ]/[H 3 O + ] ratio where global coupling by migration helps sustain the flux of Cu 2+ to actively growing surface sections. Bottom-up superfilling relies on positive feedback whereby inhibition provided by adsorption of the polyether additive on the chloride saturated surface is disrupted by the metal deposition reaction. Release of the water of hydration that accompanies reduction of the Cu 2+ aquo complex contributes to the sustained disruption of suppressor activity at the growth front. The correlation between TSV superfilling and additive-generated voltammetric hysteresis on planar substrates, which also involves a negativedifferential-resistance (S-NDR) coupled with the electrolyte resistance, provides a general framework for understanding and guiding optimization of the bottom-up growth mode in recessed surface features.Significant effort is presently focused on the development and optimization of economical processes for building three-dimensional microelectronic circuitry of arbitrary complexity. 1 Structures of interest range from deep sub-100 nm interconnects between individual transistors to micrometer scale through-silicon-vias (TSV) that serve as major electrical conduits in stacked chip arrays. The densification associated with three dimensional structures enabled by TSV in particular promises to enhance performance and functionality in emerging electronic devices. Superconformal copper electrodeposition is a key process used in the fabrication of all interconnects; the need for robust, void-free filling of ever higher aspect ratio, recessed features with reduced fill times and low cost remains an on-going challenge. Likewise, exploration of different TSV dimensions and geometries is central to understanding the reliability and extendability of Cu interconnect technology. [2][3][4][5] Both two 6 (suppressor-accelerator) and three 7 (suppressoraccelerator-leveler) additive component chemistries previously used for on-chip Damascene metallization [8][9][10][11][12] have been shown to be viable for TSV filling. Herein we show that bottom-up TSV filling may also be accomplished using a single component polyether suppressor chemistry. The polyether suppressor additive blocks metal deposition on the free surface and via side walls while rapid Cu deposition proceeds almost exclusively from the bottom surface, giving rise to bottom-up superfilling....