Pattern matching and refinement hybrid approach to circuit comparison

Abstract

We present a new approach to circuit comparison which was developed to combine general applicability with most of the advantages of hierarchical processing. Two reasons often prevent hierarchical cell by cell comparison: hierarchical circuit extraction cannot be performed in all cases and if so, the resulting hierarchy is often non-isomorphic to the schematic hierarchy. Therefore, general applicability requires the ability to cope with flat circuits. Consequently, many tools compare flat netlists of transistors or logic gates. On the other hand, apart from the speed-up, hierarchical processing is superior in terms of error localization and functional but not topological isomorphism. Our objective was to develop a tool which exploits the latter two advantages of hierarchical processing, while not sacrificing general applicability. The basic principle of operation is the pattern matching of arbitrary subcircuits in larger circuits

External memory layout vs. schematic

“…(The latter is possibly due to internal matrix representations of intermediate stages of matching [Luellau et al 1984;Rubanov 2003;Ullmann 1976]). On the contrary there are some algorithms that are fast on common subgraphs [Ohlrich et al 1993;Yang and Shi 2003] and others that use sophisticated techniques that are very accurate in finding instances of difficult cases [Pelz and Roettcher 1994;Rubanov 2003]. …”

“…In fact, studies have shown that general subcircuit matching does not contribute to the huge running time of a program. In most cases these increased running times are caused by pathological cases like symmetric circuits, functionally-same-but-toplogically-nonisomorphic circuits and interconnection of two model graphs leading to an instance of a third model graph [Chanak 1995;Pelz and Roettcher 1994], etc. Although there are advanced special techniques to handle such cases, they are impractical on large graphs due to their matrix representation of intermediate match assignments or backtracking and depth-first search procedures, all of which are undesirable in problem sizes extending to external memory.…”

“…Since all the simple subcircuits have been matched and deleted, we are left with mostly pathological cases and boundary vertices. To this we apply advanced techniques in some predetermined order [Pelz and Roettcher 1994].…”

“…Programs for subcircuit extraction based on subgraph isomorphism include Pelz and Roettcher [1994], SubGemini [Ohlrich et al 1993], Frosty [Yang and Shi 2003], [Rubanov 2003]. In general, the (sub)graph isomorphism approach is found to be more effective for confirming the functional verification of circuits than other techniques like simulation or rule based functional verification which require a huge amount of preprocessing and prior information.…”

Static low power verification at transistor level for SoC design

“…To achieve the reliable recognition of some particular structures, like level shifters, enable level shifters and logic gates, a graphcomparison algorithm was implemented in Python language to solve the theoretical problem of sub-graph isomorphism [10,11]. All topologies are declared in Spice syntax as sub-circuits including a set of standard devices with M, Q, C, L or R prefix, some internal nodes and external ports.…”