We present a new approach to circuit comparison which was developed to combine general applicability with most of the advantages of hierarchical processing. Two reasons often prevent hierarchical cell by cell comparison: hierarchical circuit extraction cannot be performed in all cases and if so, the resulting hierarchy is often non-isomorphic to the schematic hierarchy. Therefore, general applicability requires the ability to cope with flat circuits. Consequently, many tools compare flat netlists of transistors or logic gates. On the other hand, apart from the speed-up, hierarchical processing is superior in terms of error localization and functional but not topological isomorphism. Our objective was to develop a tool which exploits the latter two advantages of hierarchical processing, while not sacrificing general applicability. The basic principle of operation is the pattern matching of arbitrary subcircuits in larger circuits

We present a new approach to circuit comparison and building-block recognition. In contrast to conventional systems, we employ netlist pattern matching as the basic feature, allowing to identify arbitrary subcircuits in larger circuits. Typically, a hierarchical netlist derived from a schematic and a flat netlist extracted from a layout have to be compared. In our approach, this is accomplished by the successive (bottom up) matching of the schematic cells in layout-netlist, thus restoring the schematic hierarchy. The pattern matching algorithm is embedded in a sophisticated hierarchy handling scheme, allowing to process even ill-structured hierarchies. Our method is independent from circuit technology and design style. Typical drawbacks of traditional systems as the handling of parallel pathes or the permutability of (groups of) terminals are overcome in a quite natural way

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