Patterning effect and correlated electrical model of post-OPC MOSFET devices

Cheng, Yuhua; Ou, Tianjian; Wu, Meng-Hsu; Wang, W. L.; Feng, Junhong; Huang, Wen‐Shih; Lai, Ching-Ming; Liu, R. G.; Ku, Yao-Ching

doi:10.1117/12.717254

Cited by 5 publications

(3 citation statements)

References 1 publication

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“…It is shown that the hydrodynamic-based model under-predicts the local hotspot [4][5], typically 13% in 90 nm gate-length device [4]. It is also presented that the non-rectangular nature of the device structure becomes important for such shorter device [6]. These works exhibited the importance of applying special treatment for the hotspot discussions for devices with typically less than 100 nm, importance of BTE model and device structure.…”

mentioning

confidence: 94%

Scaling consideration on local hotspot for Si MOSFETs - for device length scale typically larger than 100 nm

Fushinobu

Yamamoto

Hatakeyama

2010

2010 12th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems

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Non-equilibrium thermal characteristics in Si MOSFETs are considered. Both lumped and rigorous electro-thermal model are deployed to examine the device lattice and electron temperatures. Non-equilibrium nature of electrons and phonons becomes important for devices with gate length typically shorter than 10 -6 m. Lumped model cannot capture the local heat generation distribution at the device level. Further discussion on the heat generation characteristics revealed that the hotspot predictions of devices typically shorter than 200 nm needs different strategy from larger devices. KEY WORDS: Si MOSFET, Length scale, NOMENCLATURE J current density, A/m 2 L gate length, m N, n, p number density, electron, hole number density, m -3 P heat dissipation rate, W q unit charge, C T temperature, K t ox oxide thickness, m V voltage, V v velocity, m/s W gate width, m x, y spatial coordinate, m Greek symbols ε 0 permeability of vacuum, F/m ε ox dielectric constant of gate oxide ε Si dielectric constant of gate oxide κ thermal conductivity ∝ mobility, m 2 /(V-s) φ potential, V Subscripts A acceptor a average in the device area D drain, donor e electron h hole G gate L lattice S source INTRODUCTIONFeature size of the current silicon MOSFETs are entering the sub-40 nm length scale, and the CMOS devices are expected to play a continuing key role in the semiconductor industries. Energy and thermal management for the CMOS devices are becoming more and more important due to the increasing demand for the energy savings of the ICT equipment. It must be pointed out that the energy and thermal management has to be considered at different length scales due to their governing physics. System level energy and thermal management including high performance cooling technology play a crucial role to control the system level temperature profile to govern the equipment design. Sub-micron scale device level energy and thermal management, on the other hand, determine two important features in operating devices: the heat dissipation and the intensity of the local hotspot (device-level temperature rise due to the self-heating.) The intensity is mainly governed by the heat generation and by the local heat conduction. It gives additional temperature rise of the devices that cannot be controlled by the system level energy and thermal management. In order to discuss the local hotspot, it is important to review the nature of heat generation, the local self-heating characteristics. Pop et al.[1] has reviewed the trend in the heat generation and transport in nanoscale transistors. Rowlette and Goodson [2] have discussed the coupling electron and phonon transport model for the heat conduction in nanoscale silicon-based devices. Phonon transport models for hotspot predictions have been reviewed by Narumanchi et al. [3]. These papers have exhibited the importance of applying Boltzmann Transport Equation (BTE)-based analysis for silicon MOSFETs with typical length smaller than 100 nm. It is shown that the hydrodynamic-based model under-predicts the local hotspot...

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mentioning

confidence: 94%

Scaling consideration on local hotspot for Si MOSFETs - for device length scale typically larger than 100 nm

Fushinobu

Yamamoto

Hatakeyama

2010

2010 12th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems

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“…Based on TCAD simulation results, we found that S can be modeled as a linear function of θ, f (θ) = (a + bθ) * L ef f /L ef f −ref . 1 Parameters a and b are obtained from TCAD simulation results and their values are 8nm and 0.089nm/degree, respectively. Since horizontal field changes linearly with channel length, it is modeled by a multiplier,…”

Section: A Channel Lengthmentioning

confidence: 99%

“…Even with various resolution enhancement techniques and design for manufacturability methodology, significant lithography pattern distortion is observed on polysilicon and diffusion layers [1,2].…”

Section: Introductionmentioning

confidence: 99%

On Electrical Modeling of Imperfect Diffusion Patterning

Chan

Gupta

2010

2010 23rd International Conference on VLSI Design

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Imperfect lithographic patterning leads to nonrectangular polysilicon and diffusion layers. Though electrical modeling of polysilicon rounding has received much attention, same is not true for diffusion. In this work, we propose the first physically derived electrical model for diffusion rounding. We show that channel length, effective device width and V th of the device are affected. The model shows that effect of rounding is not symmetric with respect to source and drain. Further, we extend the model to handle polysilicon and diffusion patterning imperfections together. The model can be calibrated using circuit simulation instead of silicon/TCAD. The average errors (as verified with TCAD simulation) of the model are 1.6% and 1.7% for TCAD and SPICE based calibration respectively. The average error for the combined poly and diffusion rounding model is 2.7%. As a simple circuit application, we show that poly-to-diffusion spacing rule can be shrunk to reduce cell area by 5% without any delay or leakage penalty.

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A new method to improve accuracy of leakage current estimation for transistors with non-rectangular gates due to sub-wavelength lithography effects

Tsai

You

et al. 2008

2008 IEEE/ACM International Conference on Computer-Aided Design

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Patterning effect and correlated electrical model of post-OPC MOSFET devices

Cited by 5 publications

References 1 publication

Scaling consideration on local hotspot for Si MOSFETs - for device length scale typically larger than 100 nm

Scaling consideration on local hotspot for Si MOSFETs - for device length scale typically larger than 100 nm

On Electrical Modeling of Imperfect Diffusion Patterning

A new method to improve accuracy of leakage current estimation for transistors with non-rectangular gates due to sub-wavelength lithography effects

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