Patterning process exploration of metal 1 layer in 7nm node with 3D patterning flow simulations

Gao, Weimin; Ciofi, Ivan; Saad, Yves; Matagne, Philippe; Bachmann, Michael; Oulmane, Mohamed; Gillijns, Werner; Lucas, Kevin; Demmerle, Wolfgang; Schmoeller, Thomas

doi:10.1117/12.2085328

Cited by 3 publications

(2 citation statements)

References 11 publications

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“…Such analysis was conducted by Gao et al, 27 who evaluated printing of a smaller M1 pattern by both 193i and EUV lithography. Such analysis was conducted by Gao et al, 27 who evaluated printing of a smaller M1 pattern by both 193i and EUV lithography.…”

Section: Analysis and Summarymentioning

confidence: 99%

Lithographic imaging-driven pattern edge placement errors at the 10-nm node

Tyminski

Sakamoto

Palmer

et al. 2016

J. Micro/Nanolith. MEMS MOEMS

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As new microelectronic designs are being developed, the demands on image overlay and pattern dimension control are compounded by requirements that pattern edge placement errors (EPEs) be at a single-nanometer levels. Scanner performance plays a key role in determining location of the pattern edges at different device layers, not only through overlay but also through imaging performance. The imaging contributes to edge displacement through the variations of the image dimensions and by shifting the images from their target locations. We discuss various aspects of advanced image control relevant to a 10-nm node integrated circuit design. We review a range of issues of pattern edge placement directly linked to pattern imaging. We analyze the impact of different pattern design and scanner-related edge displacement drivers. We present two examples of imaging strategies to pattern logic device metal layer cuts. We analyze EPEs of the cut images resulting from optimized layout design and scanner setup, and we draw conclusions on edge placement control versus imaging performance requirements. Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 06/24/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx J. Micro/Nanolith. MEMS MOEMS 021402-8 Apr-Jun 2016 • Vol. 15(2) Tyminski et al.: Lithographic imaging-driven pattern edge placement errors at the 10-nm node Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 06/24/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx J. Micro/Nanolith. MEMS MOEMS 021402-10 Apr-Jun 2016 • Vol. 15(2) Tyminski et al.: Lithographic imaging-driven pattern edge placement errors at the 10-nm node Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 06/24/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

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Section: Analysis and Summarymentioning

confidence: 99%

Lithographic imaging-driven pattern edge placement errors at the 10-nm node

Tyminski

Sakamoto

Palmer

et al. 2016

J. Micro/Nanolith. MEMS MOEMS

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“…With the introduction of EUV lithography in high volume manufacturing, stochastic effects such as photon shot noise, secondary scattering, and the interaction amongst the finite number of chemical molecules (inhibitor, PAG, quencher) during post exposure bake (PEB) contribute significantly to variability and impact the lithographic process window. Simulation studies have been used to investigate the impact of stochastics and overlay errors on device performance, for instance to assess dielectric reliability requirements in terms of time-dependent dielectric breakdown (TDDB) characteristics [2].…”

Section: Introductionmentioning

confidence: 99%

Electrical analysis of a stochastically simulated 2 nm node electrical test structure

Melvin¹,

Demmerle

Siebert

et al. 2023

DTCO and Computational Patterning II

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Integrated circuit performance has been limited by transistor performance for many process nodes. However, in advanced nodes where pitches reach 10s of nanometers in size, there is an increasing probability of cases where circuit timing may be limited by the resistance and capacitance of the device rather than the transistor. This means that metal layer patterning may have implications on device performance beyond reliability, shorts, and opens. Lithography variation can be effectively predicted using stochastic simulations, including layer overlay. Simulating many patterns stochastically produces insight into the performance of the lithography process over time. Etching and metallizing the pattern set in simulation then allows the study to extend to electrical simulations. The combined lithography and electrical simulation data can then be used together to improve process or pattern performance before constructing a reticle. These data also allow the engineering teams to address resist and capacitance issues that may impact device performance prior to tapeout. This paper will investigate the metal layers of a structure designed to emulate an advanced node logic circuit that uses a CFET transistor. The structure will be corrected with OPC, and each layer will be simulated to generate a large (100) set of stochastic patterns at multiple process conditions in focus, overlay, and exposure. Each of these patterns will then be etched in a modeled process and metalized with copper. Finally, resistance and capacitance measurements will be generated from circuit simulations. The output data will then be used to update the lithography process or the pattern to improve through process performance including electrical characteristics.

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