2001
DOI: 10.1109/16.918251
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Patterning sub-30-nm MOSFET gate with i-line lithography

Abstract: We have investigated two process techniques: resist ashing and oxide hard mask trimming. A combination of ashing and trimming produces sub-30-nm MOSFET gate. These techniques require neither specific equipment nor materials. These can be used to fabricate experimental devices with line width beyond the limit of optical lithography or high-throughput-beam lithography. They provide 25-nm gate pattern with-line lithography and sub-20-nm pattern with-beam lithography. A 40-nm gate channel length nMOSFET is demonst… Show more

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Cited by 33 publications
(13 citation statements)
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“…As is shown in Fig. 2(a), the increase of the ashing rate was observed if the reaction power was raised regardless of PR type, and this phenomenon is similar to the results reported by K. Asano et al [14]. However, the ashing rate of PMMA is higher than that of AZ1512: For example, the ashing rate of PMMA was approximately 4 nm/s at 200 W. On the other hand, the ashing rate of AZ1512 was approximately 3.3 nm/s even at high reaction power (300 W).…”
Section: Experiment: Formation Of Nanoelectrodessupporting
confidence: 91%
“…As is shown in Fig. 2(a), the increase of the ashing rate was observed if the reaction power was raised regardless of PR type, and this phenomenon is similar to the results reported by K. Asano et al [14]. However, the ashing rate of PMMA is higher than that of AZ1512: For example, the ashing rate of PMMA was approximately 4 nm/s at 200 W. On the other hand, the ashing rate of AZ1512 was approximately 3.3 nm/s even at high reaction power (300 W).…”
Section: Experiment: Formation Of Nanoelectrodessupporting
confidence: 91%
“…A 100 nm gate hard mask oxide by LPCVD was deposited and phosphorous implantation was followed for gate doping. The gate was patterned over the vertical fins by using I-line lithography with a subsequent resist ashing-hard mask oxide trimming technique [12] as shown in Fig. 8(a) and (b).…”
Section: (A) and (B)mentioning
confidence: 99%
“…By removing the sacrificial layer, the spacer can be used as a hard mask to define structures in the underlying layers. The spacer technique has been applied in order to fabricate fin field effect transistors (Fin FETs) with shorter gate length and higher performance than lithographically defined MOS FETs [15]- [18]. Devices made with the spacer technique have been deployed in other fields as well, such as optical applications [19], high-frequency transistors [20] and biosensing [21].…”
Section: A Spacer Technologymentioning
confidence: 99%