Deep-sub-tenth micron MOSFETs with gate length down to 20 nm are reported. To improve the short channel effect immunities, a novel "Folded Channel Transistor" structure is proposed. The quasi-planar nature of this new variant of the vertical double-gate SO1 MOSFETs [1], [2] simplified the fabrication process. The special features of thie structure ( Fig. 1) are: (1) a transistor is formed in a vertical ultra-thin Si fin and is controlled by a double-gate, which suppresses short channel effects; (2) the two gates are self-aligned and are aligned to the S/D; (3) S/D is raised to reduce the parasitic resistance; (4) new low-temperature gate or ultra-thin gate dielectric materials can be used because they are deposited after the S/D; and (5) the structure is quasi-planar because the Si fins are relatively short. Figure 2 shows the process flow and the SEM pictures at two fabrication steps. Using SO1 wafers as the starting material, Si3N4 and Si02 layer were deposited on the 50-nm SO1 layer. Using 100 keV EB lithography and ashing technique, -20 nm wiide Si fins were patterned and etched. Then, 100-nm P-doped a-Si and 300-nm Si02 were deposited and the result is shown in the top SEM picture. The a-Si becomes polycrystalline later and provides a good contact at the side surface of the Si fin. After delineating the a-Si S/D pattern, SiOz spacers were formed on the sidewalls of the S/D. Through sufficient over-etching, Si02 was removed from the sides of the relatively low Si fins. The top-view SEM picture shows a 15-nm thin Si fin visible in the 50-nm spacer gap, which determines the gate length. After growing 2.5-nm gate oxide on the side surfaces of the Si fin, B-in-situ-doped SiGe (60% Ge) was deposited as the gate. During the gate oxidation, P was diffused from the raised S/D into the Si fin region tlo form S/D extension. We did not use metal electrodes in this experiment so that additional S/D extension diffusion can be optimized. This explains the large parasitic resistance of over 3000 ohmldevice. The W of the devices is twice the height of the Si fins or approximately 100 nm.Typical I-V characteristics of 30-nm gate length are slhown in Fig. 3. In spite of low channel impurity concentration ( 10l6 cm-'), the leakage current caused by DIBL was well suppressed. The Vt roll-off characteristics of a 20-nm Si width devices are shown in Fig. 4. Vt is defined as the gate voltage when Ids= lo-'' A. Good roll-off characteristics are observed for folded channel structure. Figure 5 shows the subthreshold swing dependence on the: Si width. Since the thin body of the double-gate device prevents the punch-through, the folded channel devices show small swings. In Fig. 6, the transconductance (Gm) are plotted with the Si width as a parameter. Interestingly, Gm peaks at 30-nm of Si width. This is because that the thin body increases the parasitic resistance but also can increase the mobility and reduce the charge centrioid, resulting in an optimum in the Si width. Finally, to achieve high current drivability and demonstrate dis...

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A 40-nm-gate-length ultrathin-body (UTB) nMOSFET is presented with 20-nm body thickness and 2.4-nm gate oxide. The UTB structure eliminates leakage paths and is an extension of a conventional SOI MOSFET for deep-sub-tenth micron CMOS. Simulation shows that the UTB SOI MOSFET can be scaled down to 18-nm gate length with 5 nm UTB. A raised poly-Si S/D process is employed to reduce the parasitic series resistance.Index Terms-CMOS, deep-sub-tenth micron, gate work function engineering, MOSFET, raised poly-Si S/D, short-channel effect, SiGe, SOI, ultrathin-body.

High-performance PMOSFETs with sub-50-nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical double-gate SOI MOSFET features: 1) a transistor channel which is formed on the vertical surfaces of an ultrathin Si fin and controlled by gate electrodes formed on both sides of the fin; 2) two gates which are self-aligned to each other and to the source/drain (S/D) regions; 3) raised S/D regions; and 4) a short (50 nm) Si fin to maintain quasi-planar topology for ease of fabrication. The 45-nm gate-length p-channel FinFET showed an dsat of 820 A/ m at ds = gs = 1 2 V and ox = 2 5nm. Devices showed good performance down to a gate-length of 18 nm. Excellent short-channel behavior was observed. The fin thickness (corresponding to twice the body thickness) is found to be critical for suppressing the short-channel effects. Simulations indicate that the FinFET structure can work down to 10 nm gate length. Thus, the FinFET is a very promising structure for scaling CMOS beyond 50 nm.

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