Ultrathin-body SOI MOSFET for deep-sub-tenth micron era

Abstract

A 40-nm-gate-length ultrathin-body (UTB) nMOSFET is presented with 20-nm body thickness and 2.4-nm gate oxide. The UTB structure eliminates leakage paths and is an extension of a conventional SOI MOSFET for deep-sub-tenth micron CMOS. Simulation shows that the UTB SOI MOSFET can be scaled down to 18-nm gate length with 5 nm UTB. A raised poly-Si S/D process is employed to reduce the parasitic series resistance.Index Terms-CMOS, deep-sub-tenth micron, gate work function engineering, MOSFET, raised poly-Si S/D, short-channel effect, SiGe, SOI, ultrathin-body.

The advancement of silicon-on-insulator (SOI) devices and their basic properties

“…The fullydepleted (FD) SOI MOSFET with ultra-thin silicon body is one of the most popular transistor architectures for ultimate scaling of CMOS devices [10,12,15,105,112,113]. Though there is no strict definition, the concept of ultra-thin-body (UTB) SOI MOSFETs is usually referred to SOI devices with silicon film thickness in the channel region 20 nm [10,112,117]. Using the ultra-thin Si films in SOI MOSFETs provides effective suppression of the short-channel effects without need of high channel doping.…”

“…[1][2][3][4][5][6][7][8]. In the recent two decades, the rapid development of SOI CMOS device technology has been primarily driven by its ability to overcome the fundamental obstacles that arise in bulk Si CMOS technology in MOSFET downsizing to nanometer dimensions [9][10][11][12][13][14][15][16][17][18], and also to reduce device operation voltage and power consumption, which makes it very attractive for modern computing and communication systems [19][20][21][22][23][24][25][26].…”

“…One is that SOI wafers have become commercially available and less expensive. The other is related to the fact that by this time bulk Si CMOS technology reached its limit in terms of MOSFET miniaturization, and the use of SOI technology made it possible to continue reducing the MOSFET's length down to L g  10 nm gate length [9][10][11][13][14][15][16][17][18]. One more important reason for the sharp increase of SOI market is growing use of SOI in consumer portable and mobile electronic devices, such as laptops, mobile phones, smartphones, etc., which require high-speed, low-voltage and low-power operation [23][24][25][26][27].…”

Two-Dimensional-Like Amorphous Indium Tungsten Oxide Nano-Sheet Junctionless Transistors with Low Operation Voltage

“…As devices scaling continues, Si-based ultra-thin body (UTB) field-effect transistors (FETs) and FinFET with low leakage currents and good gate controllability allow gate/channel length reduction through Fin (body) thickness scaling 1,2 . Furthermore, the single crystalline silicon (Si)/polycrystalline silicon (poly-Si)-based nanowires (NWs) and nano-sheet (NS) junctionless (JL) devices with low operation voltage and near ideal subthreshold characteristics have been proposed and demonstrated for lower thermal budgets and easier processes 3–6 .…”

Structural Optimization of Wavy FinFET for Leakage Reduction and Performance Enhancement

“…A layered silicon-insulator-silicon substrate replaced conventional silicon substrates to form SOI technology [4]. The ultrathin body FET eliminates the leakage paths between source and drain , and thereby control short-channel effects with thin body [5]. Multiple gate devices such as double gate, trigate, pi-gate, GAA devices could achieve better gate control over channel [6].…”