Sub-50 nm P-channel FinFET

Abstract

High-performance PMOSFETs with sub-50-nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical double-gate SOI MOSFET features: 1) a transistor channel which is formed on the vertical surfaces of an ultrathin Si fin and controlled by gate electrodes formed on both sides of the fin; 2) two gates which are self-aligned to each other and to the source/drain (S/D) regions; 3) raised S/D regions; and 4) a short (50 nm) Si fin to maintain quasi-planar topology for ease of fabrication. The 45-nm gate-length p-channel FinFET showed an dsat of 820 A/ m at ds = gs = 1 2 V and ox = 2 5nm. Devices showed good performance down to a gate-length of 18 nm. Excellent short-channel behavior was observed. The fin thickness (corresponding to twice the body thickness) is found to be critical for suppressing the short-channel effects. Simulations indicate that the FinFET structure can work down to 10 nm gate length. Thus, the FinFET is a very promising structure for scaling CMOS beyond 50 nm.

Thickness-Dependence Electrical Characterization of the One-Dimensional van der Waals TaSe3 Crystal

“…The demand for novel device architecture and materials has been increasing tremendously due to the physical limitations of the current Si-based semiconductor technology, which arise as the size of a single transistor decreases to nanometer size [1,2,3,4]. Even though the issues arising from high-density integration in electronic manufacturing have been partly solved using a three-dimensional (3D) gate structure, more fundamental solutions should be proposed to meet the requirements for the new era of artificial intelligence technology, for which quicker data processing with a small amount of energy is required [5,6,7,8,9].…”

Nondestructive hole doping enabled photocurrent enhancement of layered tungsten diselenide

“…With the rapid development of integrated circuit (IC), the channel length approaches to sub-5 nm scale, making the short channel effects severe in electronic devices [1][2][3]. Theoretical study shows that selection of large bandgap semiconductor with ultrathin thickness is essential to minimize the short channel effects [4].…”

Temperature Dependence of Electrical Parameters of Silicon-on-Insulator Triple Gate n-Channel Fin Field Effect Transistor

“…For FinFET, the body thickness T Fin should be approximately half of the gate length L G to provide better control of short channel effects. When the L G /T FIN ratio is smaller than 1.5, the drain induced barrier lowering, subthreshold swing, and leakage current are increased sensibly [2][3][4][5][6][7][8].…”

“…FinFET (Fin field-effect transistor) has been introduced as a novel device structure for all production companies such as TSMC, Intel, and Samsung to obtain a high performance of microprocessors beyond the barrier of 14 nm [1,2]. Compared to conventional MOSFET (metal oxide semiconductor field effect transistor), the FinFET provides a better electrical control over the channel, thus leading to significant improvements of device performance [1][2][3]. For FinFET, the body thickness T Fin should be approximately half of the gate length L G to provide better control of short channel effects.…”