PC-Mesh: A Dynamic Parallel Concentrated Mesh

Camacho, Jesús; Flich, José; Roca, Antoni; Duato, J.

doi:10.1109/icpp.2011.21

Cited by 7 publications

(8 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In contrast, we take a holistic approach to adaptively and proactively manage the traffic and enable the entire router to enter low power state. Researchers also proposed more sophisticated topologies, e.g., Parallel Concreted Mesh (PC-Mesh) [7] and Homogeneous Parallel Concentrated Mesh (HPC-Mesh) [6] that enable richer connections thus providing more opportunities for power saving and fault tolerance.…”

Section: Related Workmentioning

confidence: 99%

Energy-efficient interconnect via Router Parking

Samih

Ren

Krishna

et al. 2013

2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)

View full text Add to dashboard Cite

The increase in on-chip core counts in Chip MultiProcessors (CMPs) has led to the adoption of interconnects such as Mesh and Torus, which consume an increasing fraction of the chip power. Moreover, as technology and voltage continue to scale down, static power consumes a larger fraction of the total power; reducing it is increasingly important for energy proportional computing. Currently, processor designers strive to send under-utilized cores into deep sleep states in order to reduce idling power and improve overall energy efficiency. However, even in state-of-the-art CMP designs, when a core goes to sleep the router attached to it remains active in order to continue packet forwarding. In this paper, we propose Router Parking -selectively power-gating routers attached to parked cores. Router Parking ensures that network connectivity is maintained, and limits the average interconnect latency impact of packet detouring around parked routers. We present two Router Parking algorithms -an aggressive approach to park as many routers as possible, and a conservative approach that parks a limited set of routers in order to keep the impact on latency increase minimal. Further, we propose an adaptive policy to choose between the two algorithms at run-time. We evaluate our algorithms using both synthetic traffic as well as real workloads taken from SPEC CPU2006 and PARSEC 2.1 benchmark suites. Our evaluation results show that Router Parking can achieve significant savings in the total interconnect energy (average of 32%, 40% and 41% for the synthetic, SPEC CPU2006, and PARSEC 2.1 workloads, respectively).

show abstract

Section: Related Workmentioning

confidence: 99%

Energy-efficient interconnect via Router Parking

Samih

Ren

Krishna

et al. 2013

2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)

View full text Add to dashboard Cite

show abstract

“…10 Heterogeneous multiple physical networks with different channel widths and router capabilities are proved to be able to provide better performance with fine-grained flit processing. On the other hand, multiple The baseline homogeneous CMesh interconnection has been widely studied in previous papers, including multiple physical networks.…”

Section: Heterogeneous Dual-net Cmesh With Virtual Circuit Tree Multimentioning

confidence: 99%

“…However, the router complexity and power consumption are increased because of the extra links. A dynamic parallel concentrated mesh is discussed in the study of Camacho et al10 Four parallel concentrated meshes are implemented while only 1 is always activated. The cost is higher router radix, and the communication length is not necessarily short, especially for physical-adjacent cross-router PEs.…”

mentioning

confidence: 99%

PEN: a power law–enhanced network design for high efficiency multicore architecture

Leppänen

2016

Concurrency and Computation

View full text Add to dashboard Cite

We propose a heterogeneous on-chip interconnection aiming at high efficiency multicore processors. An ideal on-chip interconnection should have low latency, high throughput, low power consumption, and high scalability. However, these metrics are usually contradictory with each other. Besides, a design should focus on the requirements of real applications. We investigate the characteristics of several parallel applications. It is found that the distribution of traffic is similar as the power law. We also discovered hot spot traffic, as well as bursty traffic from applications.Meanwhile, the average injection rate of parallel applications is relatively low. The proposed network is based on a dual-net concentrated mesh, where 2 physical networks are implemented for processing different messages and improve throughput. A diagonal interconnection is used in the central part of the network for alleviating the traffic hot spot without significant hardware overhead. We evaluate the proposed design with synthetic traffic and real applications by using a simulator. Results indicate that, on average for 8 applications, the network latency of the proposed design has reduced by 32% compared with regular mesh. Concerning efficiency when executing applications, the average energy delay product of the proposed design is 52.7% and 29.7% better than mesh and concentrate mesh, respectively.

show abstract

“…PC-Mesh [Camacho et al, 2011] is another extended version of the CMesh network. The PC-Mesh network uses some other 2D-mesh networks to connect groups of four adjacent nodes which are not grouped in the original CMesh network yet.…”

mentioning

confidence: 99%

Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

Pham‐Quoc¹,

Heisswolf²,

Werner³

et al. 2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

View full text Add to dashboard Cite

Heterogeneous multicore systems are becoming increasingly important as the need for computation power grows, especially when we are entering into the big data era. As one of the main trends in heterogeneous multicore, hardware accelerator systems provide application specific hardware circuits and are thus more energy efficient and have higher performance than general purpose processors, while still providing a large degree of flexibility. However, system performance dose not scale when increasing the number of processing cores due to the communication overhead which increases greatly with the increasing number of cores. Although data communication is a primary anticipated bottleneck for system performance, the interconnect design for data communication among the accelerator kernels has not been well addressed in hardware accelerator systems. A simple bus or shared memory is usually used for data communication between the accelerator kernels. In this dissertation, we address the issue of interconnect design for heterogeneous hardware accelerator systems.Evidently, there are dependencies among computations, since data produced by one kernel may be needed by another kernel. Data communication patterns can be specific for each application and could lead to different types of interconnect. In this dissertation, we use detailed data communication profiling to design an optimized hybrid interconnect that provides the most appropriate support for the communication pattern inside an application while keeping the hardware resource usage for the interconnect minimal. Firstly, we propose a heuristicbased approach that takes application data communication profiling into account to design a hardware accelerator system with a custom interconnect. A number of solutions are considered including crossbar-based shared local memory, direct memory access (DMA) supporting parallel processing, local buffers, and hardware duplication. This approach is mainly useful for embedded system where the hardware resources are limited. Secondly, we propose an automated hybrid interconnect design using data communication profiling to define an optimized interconnect for accelerator kernels of a generic hardware accelerator system. The hybrid interconnect consists of a network-on-chip (NoC), vii viii ABSTRACT shared local memory, or both. To minimize hardware resource usage for the hybrid interconnect, we also propose an adaptive mapping algorithm to connect the computing kernels and their local memories to the proposed hybrid interconnect. Thirdly, we propose a hardware accelerator architecture to support streaming image processing. In all presented approaches, we implement the approach using a number of benchmarks on relevant reconfigurable platforms to show their effectiveness. The experimental results show that our approaches not only improve system performance but also reduce overall energy consumption compared to the baseline systems.

show abstract

PC-Mesh: A Dynamic Parallel Concentrated Mesh

Cited by 7 publications

References 18 publications

Energy-efficient interconnect via Router Parking

Energy-efficient interconnect via Router Parking

PEN: a power law–enhanced network design for high efficiency multicore architecture

Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

Contact Info

Product

Resources

About