PEARL: Performance analysis of ultra low power reversible logic circuits against DPA attacks

Padmini, C.; Ravindra, J. V. R.

doi:10.1109/iceeot.2016.7755539

Cited by 3 publications

(1 citation statement)

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“…Physical unclonable functions (PUFs) based on adiabatic present a viable approach for safe and low-power IoT device applications to overcome these issues. Padmini [20] presented a leakage resilient adder using dual rail, single clock adiabatic logic against differential power analysis (DPA) attacks. Single clock positive feedback adiabatic logic (SCPFAL) is introduced, which reduces energy dissipation and also produces uniform power and current traces.…”

Section: Introductionmentioning

confidence: 99%

Adiabatic technique based low power synchronous counter design

Sanadhya

Sharma

Alfilh

2023

IJECE

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<p>The performance of integrated circuits is evaluated by their design architecture, which ensures high reliability and optimizes energy. The majority of the system-level architectures consist of sequential circuits. Counters are fundamental blocks in numerous very large-scale integration (VLSI) applications. The T-flip-flop is an important block in synchronous counters, and its high-power consumption impacts the overall effectiveness of the system. This paper calculates the power dissipation (PD), power delay product (PDP), and latency of the presented T flip-flop. To create a 2-bit synchronous counter based on the novel T flip-flops, a performance matrix such as PD, latency, and PDP is analyzed. The analysis is carried out at 100 and 10 MHz frequencies with varying temperatures and operating voltages. It is observed that the presented counter design has a lesser power requirement and PDP compared to the existing counter architectures. The proposed T-flip-flop design at the 45 nm technology node shows an improvement of 30%, 76%, and 85% in latency, PD, and PDP respectively to the 180 nm node at 10 MHz frequency. Similarly, the proposed counter at the 45 nm technology node shows 96% and 97% improvement in power dissipation, delay, and PDP respectively compared to the 180 nm at 10 MHz frequency.</p>

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Section: Introductionmentioning

confidence: 99%