Pebble: A language for parametrised and reconfigurable hardware design

Luk, Wayne; McKeever, Steve

doi:10.1007/bfb0055228

Cited by 54 publications

(44 citation statements)

References 9 publications

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“…It has even been contended that the most efficient hardware implementation of an algorithm is one that supports a variety of finite precision representations of different sizes for its internal variables [158]. In this spirit, many commercial and research efforts have employed parameterized design style for intellectual property (IP) cores [162][163][164][165][166]. This parameterization capability not only facilitates reuse of design cores, but also allows them to be reconfigured to meet design requirements.…”

Section: Parameterized Architectural Designmentioning

confidence: 99%

High-Performance 3D Image Processing Architectures for Image-Guided Interventions

Dandekar¹

2008

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Minimally invasive image-guided interventions (IGIs) are time and cost efficient, minimize unintended damage to healthy tissues, and lead to faster patient recovery. Advanced three-dimensional (3D) image processing is a critical need for navigation during IGIs. However, achieving on-demand performance, as required by IGIs, for these image processing operations using software-only implementations is challenging because of the sheer size of the 3D images, and memory and compute intensive nature of the operations. This dissertation, therefore, is geared toward developing high-performance 3D image processing architectures, which will enable improved intraprocedural visualization and navigation capabilities during IGIs.In this dissertation we present an architecture for real-time implementation of 3D filtering operations that are commonly employed for preprocessing of medical images. This architecture is approximately two orders of magnitude faster than corresponding software implementations and is capable of processing 3D medical images at their acquisition speeds. Report Documentation PageCombining complementary information through registration between pre-and intraprocedural images is a fundamental need in the IGI workflow. Intensity-based deformable registration, which is completely automatic and locally accurate, is a promising approach to achieve this alignment. These algorithms, however, are extremely compute intensive, which has prevented their clinical use. We present an FPGA-based architecture for accelerated implementation of intensity-based deformable image registration. This high-performance architecture achieves over an order of magnitude speedup when compared with a corresponding software implementation and reduces the execution time of deformable registration from hours to minutes while offering comparable image registration accuracy.Furthermore, we present a framework for multiobjective optimization of finite-precision implementations of signal processing algorithms that takes into account multiple conflicting objectives such as implementation accuracy and hardware resource consumption. The evaluation that we have performed in the context of FPGA-based image registration demonstrates that such an analysis can be used to enhance automated hardware design processes, and efficiently identify a system configuration that meets given design constraints. In addition, we also outline two novel clinical applications that can directly benefit from these developments and demonstrate the feasibility of our approach in the context of these applications. These advances will ultimately enable integration of 3D image processing into clinical workflow.

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Section: Parameterized Architectural Designmentioning

confidence: 99%

High-Performance 3D Image Processing Architectures for Image-Guided Interventions

Dandekar¹

2008

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“…Besides the very popular Verilog and VHDL, several hardware description languages based on Java [1], Lola [4], C [5], ML [6], and Ruby [8] have been proposed. There are also new languages like Pebble [9].…”

Section: B Performance Of Vhdl Implementationmentioning

confidence: 99%

Generating hardware from OpenMP programs

Leow

Wong

2006

2006 IEEE International Conference on Field Programmable Technology

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Abstract-Various high level hardware description languages have been invented for the purpose of improving the productivity in the generation of customized hardware. Most of these languages are variants, usually parallel versions, of popular software programming languages. In this paper, we describe our effort to generate hardware from OpenMP, a software parallel programming paradigm that is widely used and tested. We are able to generate FPGA hardware from OpenMP C programs via synthesizable VHDL and Handel-C. We believe that the addition of this medium-grain parallel programming paradigm will bring additional value to the repertoire of hardware description languages.

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“…Reconfigurable computing, on the other hand, requires a hardware design process with a user interface similar to high-level programming languages. As a response to this gap researchers developed general purpose programming languages for FPGAs such as HandelC [4], JHDL [8], and Pebble [6]. To achieve high-performance circuits, a program for FPGAs needs to express a functional view just like microprocessor programs, but also a physical view corresponding to the architecture of the FPGA circuit.…”

Section: B Design Environments For Reconfigurable Computingmentioning

confidence: 99%

Object-oriented domain specific compilers for programming FPGAs

Mencer

Platzner

Morf³

et al. 2001

IEEE Trans. VLSI Syst.

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Abstract-Simplifying the programming models is paramount to the success of reconfigurable computing with field programmable gate arrays (FPGAs). This paper presents a methodology to combine true object-oriented design of the compiler/CAD tool with an object-oriented hardware design methodology in C++. The resulting system provides all the benefits of object-oriented design to the compiler/CAD tool designer and to the hardware designer/programmer. The two examples for domain-specific compilers presented are BSAT and StReAm. Each domain-specific compiler is targeted at a very specific application domain, such as applications that accelerate Boolean satisfiability problems with BSAT, and applications which lend themselves for implementation as a stream architecture with StReAm. The key benefit of the presented domain specific compilers is a reduction of design time by orders of magnitude while keeping the optimal performance of hand-designed circuits.

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Pebble: A language for parametrised and reconfigurable hardware design

Cited by 54 publications

References 9 publications

High-Performance 3D Image Processing Architectures for Image-Guided Interventions

High-Performance 3D Image Processing Architectures for Image-Guided Interventions

Generating hardware from OpenMP programs

Object-oriented domain specific compilers for programming FPGAs

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