PEEC based parasitic modeling for power analysis on custom rotary rings

Abstract

Resonant rotary clocking is a low power-high speed clock distribution technology for the modern VLSI circuits. Alternative topological implementations of rotary clocking with nonregular custom rings have been proposed in literature. In this paper, the impact of parasitics of the non-regular topological geometries on the rotary operating characteristics is presented. In particular, partial element equivalent circuit (PEEC) analysis is used to show that the corner geometry in a custom ring increases the mutual inductance approximately by 80%. Also, SPICE simulations are performed where the parasitics due to the topological factors are incorporated for an 8% increased accuracy in simulation. Further, the power dissipation on the rotary ring is analyzed with varying number of corners. When tested with the IBM R1-R5 benchmark circuits, the total power dissipated on a custom ring (corners between 4 and 12) is within ±5% of the total power dissipated on a regular ring(4 corners).

High-performance, low-power resonant clocking

“…Back-to-back inverters are connected to this parallel loop to compensate for the [12,15,21,30,35,39], including zero clock skew operation [14,16], interconnect modeling [13], frequency estimation [32], phase estimation and control [31,34,38], phase noise [29] and variation-sensitivity [33]. Prototype designs have been demonstrated [28,37].…”