Penryn: 45-nm next generation Intel&amp;#x00AE; core&amp;#x2122; 2 processor

George, Varghese; Jahagirdar, Sanjeev; Tong, Chao; Smits, K.; Damaraju, Satish; Siers, Scott; Naydenov, Ves; Khondker, Tanveer; Sarkar, Sanjib; Singh, Pradhumn

doi:10.1109/asscc.2007.4425784

Cited by 34 publications

(1 citation statement)

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“…In amorphous state its dielectric constant is ~20-22, (4×) higher than that of Si3N4. Moreover, it is already introduced into microelectronics [4]. It was demonstrated that HfO2 could outperform Si3N4 in terms of trap density, which makes it a strong candidate for charge trapping layer in future CT memories [5].…”

Section: Introductionmentioning

confidence: 99%

Characterization of program and erase speed of memory capacitors with nanolaminated HfO₂/Al₂O₃ stacks for application in non-volatile memories

Spassov,

Paskaleva,

Ivanov

et al. 2024

J. Phys.: Conf. Ser.

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The programming and erase performance of atomic layer deposited HfO2/Al2O3 memory stacks is investigated depending on the thickness of the tunnel oxide and the annealing of the structures. The as-grown stacks require applying of voltage pulses with duration of about 10-3 s for a measurable electron trapping (programming). The time dependence of the electron trapping process is quite sharp initially - the increase of the charging time from 4×10-4 s to 4×10-3 s provides more than 80% of the saturation value of the trapped charge obtained at durations above 1 s. The annealing increases the time needed for the onset of the electron trapping. For the chosen voltage amplitudes the programming characteristics does not depend on the tunnel oxide thickness. The electron detrapping (erase) is observed even at durations of ~10-7 s, but with a low efficiency. The erase characteristics is more gradual then the program one, and shows some dependence on tunnel oxide and annealing. The complete erase is achieved for times comparable to those for programming the cell. Erase pulses with duration > 10-2 s results to accumulation of positive charge in the capacitors.

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Section: Introductionmentioning

confidence: 99%

Characterization of program and erase speed of memory capacitors with nanolaminated HfO₂/Al₂O₃ stacks for application in non-volatile memories

Spassov,

Paskaleva,

Ivanov

et al. 2024

J. Phys.: Conf. Ser.

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Engineering Strategies in Emerging Fluorite-Structured Ferroelectrics

Park

Lee

Yang

et al. 2021

ACS Appl. Electron. Mater.

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Ferroelectricity has been increasingly applied to develop fluorite-structured oxides since its discovery in 2011. Unlike conventional ferroelectric materials, these materials are compatible with complementary metal oxide semiconductor technology with established fabrication techniques. Early stage research has focused on enhancing the ferroelectricity in solid solution films for nonvolatile data storage. Recently, engineering strategies, such as those that entail the use of morphotropic phase boundaries to achieve high permittivity and develop artificial structures such as nanolaminates/superlattices, have been suggested to enhance ferroelectricity/antiferroelectricity; such strategies have the potential to provide new pathways for advanced nanoelectronics. Furthermore, the dielectric constant, remanent polarization, and processing window applied in these strategies yield more desirable outcomes than the solid solutions. Such strategies are also believed to be applicable to the design of cell capacitors for dynamic and ferroelectric random-access memory technology. However, a comprehensive review of these ferroelectricity-related engineering strategies has not yet been reported. Thus, recently developed engineering strategies for fluorite-structured ferroelectrics are reviewed in this paper.

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A sub 2W low power IA Processor for Mobile Internet Devices in 45nm Hi-K metal gate CMOS

Gerosa

Curtis

D'Addeo

et al. 2008

2008 IEEE Asian Solid-State Circuits Conference

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This paper describes a low power Intel® Architecture (IA) processor specifically designed for Mobile Internet Devices (MID). The design consists of an in-order pipeline capable of issuing 2 instructions per cycle supporting 2 threads, 32KB instruction and 24KB data L1 caches, independent integer and floating point execution units, a 512KB L2 cache and a 533 MT/s dual-mode (GTL and CMOS) frontside-bus (FSB). The design contains 47 million transistors in a die size under 25 mm 2 manufactured in a 9-metal 45nm CMOS process. Thermal design power (TDP) consumption is measured at 2W, 1.0V, 90 o C using a synthetic power-virus test at a frequency of 1.86GHz.

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Penryn: 45-nm next generation Intel® core™ 2 processor

Cited by 34 publications

References 1 publication

Characterization of program and erase speed of memory capacitors with nanolaminated HfO₂/Al₂O₃ stacks for application in non-volatile memories

Characterization of program and erase speed of memory capacitors with nanolaminated HfO₂/Al₂O₃ stacks for application in non-volatile memories

Engineering Strategies in Emerging Fluorite-Structured Ferroelectrics

A sub 2W low power IA Processor for Mobile Internet Devices in 45nm Hi-K metal gate CMOS

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Penryn: 45-nm next generation Intel&#x00AE; core&#x2122; 2 processor

Cited by 34 publications

References 1 publication

Characterization of program and erase speed of memory capacitors with nanolaminated HfO2/Al2O3 stacks for application in non-volatile memories

Characterization of program and erase speed of memory capacitors with nanolaminated HfO2/Al2O3 stacks for application in non-volatile memories

Engineering Strategies in Emerging Fluorite-Structured Ferroelectrics

A sub 2W low power IA Processor for Mobile Internet Devices in 45nm Hi-K metal gate CMOS

Contact Info

Product

Resources

About

Penryn: 45-nm next generation Intel® core™ 2 processor

Characterization of program and erase speed of memory capacitors with nanolaminated HfO₂/Al₂O₃ stacks for application in non-volatile memories

Characterization of program and erase speed of memory capacitors with nanolaminated HfO₂/Al₂O₃ stacks for application in non-volatile memories