Performance analysis and simulation of vertical gallium nitride nanowire transistors

Witzigmann, Bernd; Feng, Yuqing; Frank, Kristian; Strempel, Klaas; Fatahilah, Muhammad Fahlesa; Schumacher, H. W.; Wasisto, Hutomo Suryo; Römer, Friedhard; Waag, A.

doi:10.1016/j.sse.2018.03.005

Cited by 13 publications

(5 citation statements)

References 17 publications

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“…This value appears to be quite low for electron transport in GaN, but there is strong evidence that the mobility in the p-doped channel is lower than predicted by the mobility model [21], similar to silicon MOSFETs. The inverted p-doped channel confines electrons close to the fin sidewall interface to the gate oxide and suppresses leakage currents through the inner part of the fin as reported for npn-NW FETs [14]. The inset in figure 8(b) shows the current density near the interface at different vertical positions.…”

Section: Characterizationmentioning

confidence: 75%

“…Electrons are described by a hydrodynamic transport model, whereas holes are generally described by a drift/diffusion transport model. Details on the simulation model as well as the associated material parameters are given in a previous work [14]. The geometry of the simulation model was made to match the finFET geometry with tapered channel region shown in the FIB cross section in figure 4.…”

Section: Simulation Modelmentioning

confidence: 99%

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Vertical 3D gallium nitride field-effect transistors based on fin structures with inverted p-doped channel

Strempel

Römer

Feng

et al. 2020

Semicond. Sci. Technol.

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This paper demonstrates the first vertical field-effect transistor based on gallium nitride (GaN) fin structures with an inverted p-doped channel layer. A top-down hybrid etching approach combining inductively coupled plasma reactive ion etching and KOH-based wet etching was applied to fabricate regular fields of GaN fins with smooth a-plane sidewalls. The obtained morphologies are explained using a cavity step-flow model. A 3D processing scheme has been developed and evaluated via focussed ion beam cross-sections. The top-down approach allows the introduction of arbitrary doping profiles along the channel without regrowth, enabling the modulation of the channel properties and thus increasing the flexibility of the device concept. Here, a vertical npn-doping profile was used to achieve normally-off operation with an increased threshold voltage as high as 2.65 V. The p-doped region and the 3D gate wrapped around the sidewalls create a very narrow vertical electron channel close to the interface between dielectric and semiconductor, resulting in good electrostatic gate control, low leakage currents through the inner fin core and high sensitivity to the interface between GaN and gate oxide. Hydrodynamic transport simulations were carried out and show good agreement with the performed current–voltage and capacitance–voltage measurements. The simulation indicates a reduced channel mobility which we attribute to interface scattering being particularly relevant in narrow channels. We also demonstrate the existence of oxide and interface traps with an estimated sheet density of 3.2 × 1012 cm−2 related to the Al2O3 gate dielectric causing an increased subthreshold swing. Thus, improving the interface quality is essential to reach the full potential of the presented vertical 3D transistor concept.

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Section: Characterizationmentioning

confidence: 75%

Section: Simulation Modelmentioning

confidence: 99%

Vertical 3D gallium nitride field-effect transistors based on fin structures with inverted p-doped channel

Strempel

Römer

Feng

et al. 2020

Semicond. Sci. Technol.

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“…However, for improving the device design and performance, several strategies can be proposed for the next transistor generations, e.g., decreasing the Si-doping concentration in the drift region, integrating vertical field-plate structure, and employing longer drift region. The low doped and longer space drift region will reduce the local electric field and thus the BV can be increased 20,29,52 .…”

Section: Resultsmentioning

confidence: 99%

Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics

Fatahilah

Feng

Strempel

et al. 2019

Sci Rep

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This paper reports on the direct qualitative and quantitative performance comparisons of the field-effect transistors (FETs) based on vertical gallium nitride nanowires (GaN NWs) with different NW numbers (i.e., 1–100) and diameters (i.e., 220–640 nm) fabricated on the same wafer substrate to prove the feasibility of employing the vertical 3D architecture concept towards massively parallel electronic integration, particularly for logic circuitry and metrological applications. A top-down approach combining both inductively coupled plasma dry reactive ion etching (ICP-DRIE) and wet chemical etching is applied in the realization of vertically aligned GaN NWs on metalorganic vapor-phase epitaxy (MOVPE)-based GaN thin films with specific doping profiles. The FETs are fabricated involving a stack of n-p-n GaN layers with embedded inverted p -channel, top drain bridging contact, and wrap-around gating technology. From the electrical characterization of the integrated NWs, a threshold voltage ( V th ) of (6.6 ± 0.3) V is obtained, which is sufficient for safely operating these devices in an enhancement mode (E-mode). Aluminium oxide (Al 2 O 3 ) grown by atomic layer deposition (ALD) is used as the gate dielectric material resulting in nearly-zero gate hysteresis (i.e., forward and backward sweep V th shift (Δ V th ) of ~0.2 V). Regardless of the required device processing optimization for having better linearity profile, the upscaling capability of the devices from single NW to NW array in terms of the produced currents could already be demonstrated. Thus, the presented concept is expected to bridge the nanoworld into the macroscopic world, and subsequently paves the way to the realization of innovative large-scale vertical GaN nanoelectronics.

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“…Moreover, they have demonstrated current upscaling capability of the devices by realizing and measuring transistors with different numbers of integrated GaN nanowires on a single 2-inch wafer. A recent hydrodynamic study analyzing the performance of vertical GaN NW transistors with a non-overlapping gate structure based on the work in Yu et al [9] has been reported by Witzigmann et al [14]. In that study, the energy flux was only applied to electrons, while a drift-diffusion system was applied to holes to account for velocity overshoot effects, especially in the drift region of the transistor.…”

Section: Introductionmentioning

confidence: 99%

Investigation of Electrical Behaviors Observed in Vertical GaN Nanowire Transistors Using Extended Landauer-Büttiker Formula

et al. 2021

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Performance analysis and simulation of vertical gallium nitride nanowire transistors

Cited by 13 publications

References 17 publications

Vertical 3D gallium nitride field-effect transistors based on fin structures with inverted p-doped channel

Vertical 3D gallium nitride field-effect transistors based on fin structures with inverted p-doped channel

Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics

Investigation of Electrical Behaviors Observed in Vertical GaN Nanowire Transistors Using Extended Landauer-Büttiker Formula

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