Performance Analysis of Adaptive Resource Allocation Scheme for OpenCL-based FPGA Virtualization System

Duc-Canh, Le; Oh, Eun-Young; Cho, Gyu-Sang; Lee, KyungChae; Sung-Hyun, Kim; Youn, Chan‐Hyun

doi:10.1109/ictc46691.2019.8939758

Cited by 1 publication

(1 citation statement)

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“…Additionally, our work is limited to one dataset where a bias may exist. In the future work, it is suggested to utilize multiple datasets in order to further improve the comparison reliability [ 31 ].…”

Section: Limitations and Path Forwardmentioning

confidence: 99%

Designing Deep Learning Hardware Accelerator and Efficiency Evaluation

Chen

Siddique

2022

Computational Intelligence and Neuroscience

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With the swift development of deep learning applications, the convolutional neural network (CNN) has brought a tremendous challenge to traditional processors to fulfil computing requirements. It is urgent to embrace new strategies to improve efficiency and diminish energy consumption. Currently, diverse accelerator strategies for CNN computation based on the field-programmable gate array (FPGA) platform have been gradually explored because they have edges of high parallelism, low power consumption, and better programmability. This paper first illustrates state-of-the-art FPGA-based accelerator design by emphasizing the contributions and limitations of existing research works. Subsequently, we demonstrated significant concepts of parallel computing (PC) in the convolution algorithm and discussed how to accomplish parallelism based on the FPGA hardware structure. Eventually, with the proposed CPU+ FPGA framework, we performed experiments and compared the performance against traditional computation strategies in terms of the operation efficiency and energy consumption ratio. The results revealed that the efficiency of the FPGA platform is much higher than that of the central processing unit and graphics processing unit.

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Section: Limitations and Path Forwardmentioning

confidence: 99%