Performance Analysis of Advanced Encryption Standard on FPGA

Abstract

The Advanced Encryption Standard is the data security standard referred to as Federal Information Processing Standard 197 (FIPS 197) acquired worldwide by several private and public sectors for protective needs of data storage and secure data application from mobile consumer products to high end user. Most of the AES implementation for reconfigurable devices however based on the configurable logic such as flip-flops and lookup tables. In this paper, all the three modules i.e. AES -128, AES -192 and AES -256 are implemented on Spartan 3 XC3S1000L speed grade -4 FPGA. All the three modules are implemented with four techniques namely, sequential 3 Stage, sequential 2 stage, pipelined and combinational and then a performance of the three techniques is evaluated. At last a combined AES supporting all the three AES types is also implemented using combinational technique. It is observed from the implementations that sequential 2 stage technique is most area efficient technique, whereas pipelined technique is most time efficient technique.