Performance analysis of an efficient MAC unit using CNTFET technology

Karthikeyan, K.V.; Babu, R. Samuel Rajesh; Mathan, N.; Karthick, B.

doi:10.1016/j.matpr.2016.04.171

Cited by 5 publications

(3 citation statements)

References 11 publications

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“…This value is carried out using QCAPro software [61]. According to Table 3, the proposed MAC unit consumes less power than classical implementations [57][58][59]62]. Hence, this proposed circuit would reduce the computational complexity and the power consumption as compared to conventional logic circuits.…”

Section: Resultsmentioning

confidence: 99%

Design of efficient quantum Dot cellular automata (QCA) multiply accumulate (MAC) unit with power dissipation analysis

Gassoumi

Touil

Ouni

2019

IET Circuits, Devices & Systems

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Quantum dot cellular automata (QCA) is a hopeful technology in the field of nanotechnology that seems to suite well with signal-processing needs. It is concerned with great interest because of its benefits such as ultra-low power consumption, small size and can operate at one Terahertz. The multiply accumulator (MAC) unit is considered as one of the essential operations in digital signal processing (DSP). In the real-time DSP systems, several applications like speech processing, video coding, and digital filtering etc. require MAC operations. However, the power dissipation and area are the most significant aspects in these systems. Here, the authors design low power MAC unit based on QCA technology. QCADesigner version 2.0.3 is used to validate the accuracy of the proposed circuit. The reliability of this unit is taken at different temperatures. The power dissipation is estimated using QCAPro tool. The total power consumed by this unit is 2.183 μW. The proposed circuit has 90% improvement in terms of power over complementary metal-oxide-semiconductor (CMOS) circuits. Since the works in the field of QCA logic signal processing has started to progress, the suggested contribution will give rise to a new thread of research in the field of real-time signal and image treatment.

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Section: Resultsmentioning

confidence: 99%

Design of efficient quantum Dot cellular automata (QCA) multiply accumulate (MAC) unit with power dissipation analysis

Gassoumi

Touil

Ouni

2019

IET Circuits, Devices & Systems

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“…Although the architecture defined in [37] is implemented in 180 nm technology with a 1.8 V supply voltage for 16-MAC operation, it consumes substantially more power than the SFMAC architecture. The implementation of the architecture listed in [38] is for 1-bit unsigned fixed-point MAC operation in 32 nm CMOS & CNTFET technology, so a comparison with an 8-bit SFMAC is meaningless. Despite the fact that the architecture described in [32] is the only existing MAC architecture capable of performing on signed floating-point operations, a comparative study with the proposed SFMAC reveals that SFMAC's efficiency in terms of power consumption is much better.…”

Section: Esc Blockmentioning

confidence: 99%

An Evolutionary Normalization Algorithm for Signed Floating-Point Multiply-Accumulate Operation

Sarma¹,

Bhargava²,

Kotecha³

2022

Computers, Materials &Amp; Continua

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In the era of digital signal processing, like graphics and computation systems, multiplication-accumulation is one of the prime operations. A MAC unit is a vital component of a digital system, like different Fast Fourier Transform (FFT) algorithms, convolution, image processing algorithms, etcetera. In the domain of digital signal processing, the use of normalization architecture is very vast. The main objective of using normalization is to perform comparison and shift operations. In this research paper, an evolutionary approach for designing an optimized normalization algorithm is proposed using basic logical blocks such as Multiplexer, Adder etc. The proposed normalization algorithm is further used in designing an 8 × 8 bit Signed Floating-Point Multiply-Accumulate (SFMAC) architecture. Since the SFMAC can accept an 8-bit significand and a 3-bit exponent, the input to the said architecture can be somewhere between −(7.96872) 10 to + (7.96872) 10 . The proposed architecture is designed and implemented using the Cadence Virtuoso using 90 and 130 nm technologies (in Generic Process Design Kit (GPDK) and Taiwan Semiconductor Manufacturing Company (TSMC), respectively). To reduce the power consumption of the proposed normalization architecture, techniques such as "block enabling" and "clock gating" are used rigorously. According to the analysis done on Cadence, the proposed architecture uses the least amount of power compared to its current predecessors.

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“…The Vedic multiplier based MAC architecture in [30] has a little advantage in speed in comparison to the proposed SFMAC architecture but at the cost of very high power consumption. For the architecture mentioned in [31], the implementation is done for 1-bit unsigned fixed-point MAC operation in 32 nm CMOS and CNTFET technology and hence, comparison with 8-bit SFMAC is not relevant. Though the architecture mentioned in [25] is the only existing MAC architecture capable of performing on signed floating-point input, the comparison analysis with pro- posed SFMAC shows that the performance of SFMAC is much better in terms of power consumption.…”

Section: 1mentioning

confidence: 99%

Bulletin of the Polish Academy of Sciences: Technical Sciences

Sarma¹,

Bhargava²,

Jain³

2020

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Digital system algorithms such as FFT algorithms, convolution, image processing algorithm, etc. deploy Multiply and Accumulate (MAC) unit as an evaluative component. The efficiency of a MAC typically relies on the speed of operation, power dissipation, and chip area along with the complexity level of the circuit. In this research paper, a power-delay-efficient signed-floating-point MAC (SFMAC) is proposed using Universal Compressor based Multiplier (UCM). Instead of having a complex design architecture, a simple multiplexer-based circuit is used to achieve a signed-floating output. The 8£8 SFMAC can take 8-bit mantissa and 3-bit exponent and therefore, the input to the SFMAC can be in the range of -(7.96875) 10 to +(7.96875) 10 . The design and implementation of the proposed architecture is executed on the Cadence Spectre tool in GPDK 90 nm and TSMC 130 nm CMOS, which proves as power and delay efficient.

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Performance analysis of an efficient MAC unit using CNTFET technology

Cited by 5 publications

References 11 publications

Design of efficient quantum Dot cellular automata (QCA) multiply accumulate (MAC) unit with power dissipation analysis

Design of efficient quantum Dot cellular automata (QCA) multiply accumulate (MAC) unit with power dissipation analysis

An Evolutionary Normalization Algorithm for Signed Floating-Point Multiply-Accumulate Operation

Bulletin of the Polish Academy of Sciences: Technical Sciences

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