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CNTFET is a novel device that is projected to outperform scaled CMOS technologies.Multiplier is one of the very important hardware blocks such as FIR filters, digital signal processors etc.The performance speed of the multiplier often affects the overall speed performance in VLSI systems. On the whole, multiplication employs most of the execution time in many Digital signal processor (DSP) devices. So, high speed multiplier is greatly desired. In this paper, a high speed existing radix-4 multiplier based Shannon adder is analysed intensively. To achieve an efficient radix-4 multiplier, the proposed hybrid adder was implemented for further power reduction in high speed parallel radix-4 multiplier circuits. The proposed radix-4 multiplier is more desirable for obtaining the low power consumption, less propagation delay and efficient power delay product. Simulations are executed using Synopsys HSpice in 32nm CMOS and 32nm CNTFET Technologies. The simulation results exhibits the transcendences of the proposed structures in terms of Power consumption, propagation delay and Power delay product compared to the advanced technology of CMOS and CNTFET based designs.

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