“…Utilizing different adder implementations can improve device performance and boost the performance of digital circuits [14]. There are several full adder implementations that have been published that aim to increase performance, such as conventional complementary metal oxide semiconductors (C-CMOS) and transmission gate array (TGA) [15], transmission function array (TFA) [16], transmission gate array (TGA) [17], complementary pass transistor logic (CPL-TG) [18], full mirror adder SERF [19], 13A full adder [20], static energy recovery full adder [21], static CMOS output device and hybrid pass transistor logic (HPSC) levelrestoring, complementary, and new-(HPSC) carry logic (CLRCL) [22], double pass transistor logic [23], and hybrid CMOS logic with transmission gate logic (HCTG) [24], removed single driving full adder (RSD-FA) [25], 18 transistor 1-bit full adder (18T-FA) [26], hybrid multi threshold fault adder (HMTFA) [27], and carbon nanotube full adder (CNTAFS) [27].…”