Performance Analysis of DMG-GOS Junctionless FinFET with high-k Spacer

Kumar, Appikatla Phani; Lorenzo, Rohit

doi:10.1109/silcon55242.2022.10028902

Cited by 5 publications

(1 citation statement)

References 25 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It replaces planar CMOS in integrated circuits. FinFETs were an ideal choice because of their superior characteristics, which include less leakage power, high drain current, low switching voltage, better gate control, suppression of SCEs with the ability to operate near threshold voltages for SRAM [9]. Thin, vertical fins on the substrate make up the FinFET's structure.…”

Section: Introductionmentioning

confidence: 99%

Design of highly stable, high speed and low power 10T SRAM cell in 18-nm FinFET technology

Kumar,

Lorenzo

2023

Eng. Res. Express

Self Cite

View full text Add to dashboard Cite

Many scientists are working to develop a static random-access memory (SRAM) cell that used little power and has good stability and speed. This work introduces a fin field effect transistor developed SRAM cell with 10 transistors (10T FinFET SRAM). A cross connected standard inverter and schmitt-trigger inverter is used in the proposed 10T FinFET SRAM cell. We introduce the schmitt trigger based SRAM cell with single-ended read decoupled and feedback-cutting approaches to enhance the static noise margin (SNM) and access time of the SRAM cell. The proposed cell’s power utilization is decreased with the help of stacked N-FinFETs. For determining the relative performance of the proposed 10T FinFET SRAM cell design in terms of fundamental design metrics, it has also been compared with some of the current SRAM cells, including 6T, SBL9T SRAM, 10T SRAM, and DS10T SRAM. The simulation results at 0.6V demonstrate that the suggested design achieves low power utilization when Reading, writing and hold modes of operation in comparison to the aforementioned bit cells. It maintains a high SNM during all operations. The suggested cell is the one with fastest read access. The simulation is carried out with cadence tool using FinFET 18nm technology.

show abstract

Section: Introductionmentioning

confidence: 99%

Design of highly stable, high speed and low power 10T SRAM cell in 18-nm FinFET technology

Kumar,

Lorenzo

2023

Eng. Res. Express

Self Cite

View full text Add to dashboard Cite

show abstract

Influence of Temperature Fluctuations on the Analog and RF Characteristics of Gate-Engineered High-K Gate Dielectric Stack SOI Fin-FET

Vijaya,

Lorenzo

2023

2023 IEEE 3rd International Conference on Applied Electromagnetics, Signal Processing, &Amp; Communication (AESPC)

View full text Add to dashboard Cite

Effect of W_fin, H_fin and L_g on the performance of 14-nm FinFET for analog and RF applications

Vijaya

Lorenzo

2023

2023 International Conference on Device Intelligence, Computing and Communication Technologies, (DICCT)

View full text Add to dashboard Cite

Performance Analysis of DMG-GOS Junctionless FinFET with high-k Spacer

Cited by 5 publications

References 25 publications

Design of highly stable, high speed and low power 10T SRAM cell in 18-nm FinFET technology

Design of highly stable, high speed and low power 10T SRAM cell in 18-nm FinFET technology

Influence of Temperature Fluctuations on the Analog and RF Characteristics of Gate-Engineered High-K Gate Dielectric Stack SOI Fin-FET

Effect of W_fin, H_fin and L_g on the performance of 14-nm FinFET for analog and RF applications

Contact Info

Product

Resources

About

Performance Analysis of DMG-GOS Junctionless FinFET with high-k Spacer

Cited by 5 publications

References 25 publications

Design of highly stable, high speed and low power 10T SRAM cell in 18-nm FinFET technology

Design of highly stable, high speed and low power 10T SRAM cell in 18-nm FinFET technology

Influence of Temperature Fluctuations on the Analog and RF Characteristics of Gate-Engineered High-K Gate Dielectric Stack SOI Fin-FET

Effect of Wfin, Hfin and Lg on the performance of 14-nm FinFET for analog and RF applications

Contact Info

Product

Resources

About

Effect of W_fin, H_fin and L_g on the performance of 14-nm FinFET for analog and RF applications