Performance Analysis of <i>n</i>-Type Junctionless Silicon Nanotube Field Effect Transistor

Ambika, R.; Srinivasan, R.

doi:10.1166/jno.2016.1899

Cited by 28 publications

(3 citation statements)

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“…The device structure and its current-voltage characteristics from [6] are used for the device calibration. JLSiNT-FET device created by TCAD is given in figure 1(a), showing all the regions of the device.…”

Section: Device Structure and I D -V G Calibrationmentioning

confidence: 99%

“…The tunneling operation is realized on SiNT-FET structure in reference [5]. Junction-less operation is realized on the SiNT-FET structure (JLSiNT-FET) in the literature [6] since junction-less transistor has been appeared as one of the most expectant device due to their better immunity to short channel effects (SCEs) and well-matched process flow with the existing CMOS technologies [7].…”

Section: Introductionmentioning

confidence: 99%

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Impact of structural process variation on junctionless silicon nanotube FET

Ambika

Srinivasan²

2018

Adv. Nat. Sci: Nanosci. Nanotechnol.

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In this paper, the impact of process variation on the performance parameters of junctionless silicon nanotube field effect transistor (JLSiNT-FET) is studied using 3D numerical simulations. The performance metrics, ON current, OFF current, and unity gain frequency are taken for different physical factors. Sensitivity of the physical factors is computed over a range at various points. The ranking of the structural parameters for various performance metrics is done using a two level full factorial design of experiment method. Overall ranking proposes that the outer diameter of the silicon tube is the most sensitive parameter and inner diameter of the silicon tube is the least sensitive parameter.

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Section: Device Structure and I D -V G Calibrationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Impact of structural process variation on junctionless silicon nanotube FET

Ambika

Srinivasan²

2018

Adv. Nat. Sci: Nanosci. Nanotechnol.

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“…However, carrier mobility degrades as a result of heavy doping in the channel region, which in turn degrades the drive current and transconductance of the JL FETs [13, 14]. Subsequently, JL SiNT FET is first investigated by Ambika and Srinivasan [15]. Sahay and Kumar [16] show that JLSiNT FET offers better on‐current to off‐current ratio ( I on / I off ) and the sub‐threshold slope (SS) as compared to JLSiNW FET.…”

Section: Introductionmentioning

confidence: 99%

Enhancing the delay performance of junctionless silicon nanotube based 6T SRAM

Tayal

Nandi

2018

Micro & Nano Letters

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This work investigates the delay performance of junctionless silicon nanotube (JLSiNT) field-effect transistor (FET) based 6T SRAM cell. The study demonstrates that the delay performance of symmetric drain/source DS-JLSiNT FET (inner gate covers drain, channel, and source regions) based 6T SRAM gets improved when the inner gate of nanotube covers only either drain and channel regions (D-JLSiNT FET) or source and channel regions (S-JLSiNT FET) because of improved I on /C gg. The improvement in read (write) access time is ∼22% (17%) and ∼9% (20%) when DS-JLSiNT FET is replaced by D-JLSiNT FET and S-JLSiNT FET, respectively, in DS-JLSiNT FET based 6T SRAM. Furthermore, due to partial covering of inner gate, the gate electrostatic integrity is reduced which decreases the ratio of on-current to off-current (I on /I off) resulting in degraded static noise margin (SNM). However, the deterioration in write SNM, hold SNM, and read SNM are almost minimal (∼0.3, 0.9, and 2%, respectively) for S-JLSiNT FET based SRAM as compared to DS-JLSiNT FET based SRAM. However, the deterioration in SNMs is aggravated for D-JLSiNT FET based SRAM as compared to DS-JLSiNT FET based SRAM. Thus, S-JLSiNT FET is the best configuration for designing of JLSiNT FET based 6T SRAM cell.

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Analysis of independent gate operation in Si nano tube FET and threshold prediction model using 3D numerical simulation

Ambika¹,

Srinivasan²

2016

J Comput Electron

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Performance Analysis of n-Type Junctionless Silicon Nanotube Field Effect Transistor

Cited by 28 publications

References 0 publications

Impact of structural process variation on junctionless silicon nanotube FET

Impact of structural process variation on junctionless silicon nanotube FET

Enhancing the delay performance of junctionless silicon nanotube based 6T SRAM

Analysis of independent gate operation in Si nano tube FET and threshold prediction model using 3D numerical simulation

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