Performance analysis of Intel Core 2 Duo processor

Prakash, T.K.

doi:10.31390/gradschool_theses.43

Cited by 5 publications

(3 citation statements)

References 9 publications

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“…There are three types of cores available in S 2 , which is the major reason for the dramatic explosion in the number of configurations. Figure 5.4 plots the ideal The parameters for C2 are obtained from [117], whereas the parameters for C1 and C3 are generated by applying Pollack's rule [116] to the parameters of C2. We also assume that the smallest core, C1, implements in-order execution (IO), while the other two implement out-of-order execution (OoO).…”

Section: Resultsmentioning

confidence: 99%

“…Frequency is a parameter of exploration. To find the power and energy coefficients we employ the data obtained from [117] for the cores, CACTI 5.3 model [2] for caches and Orion 2.0 model [76] for on-chip routers and links.…”

Section: Power Modelmentioning

confidence: 99%

“…The estimates for the area of each component are derived from the parameters of the Intel Core 2 Duo E6400 processor [6]. The ideal IPC of core is obtained from [117]. We also assume that the core is out-of-order (OoO).…”

Section: Quality Of the Modelmentioning

confidence: 99%

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Automatic synthesis and optimization of chip multiprocessors

Nikitin

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The microprocessor technology has experienced an enormous growth during the last decades. Rapid downscale of the CMOS technology has led to higher operating frequencies and performance densities, facing the fundamental issue of power dissipation. Chip Multiprocessors (CMPs) have become the latest paradigm to improve the power-performance efficiency of computing systems by exploiting the parallelism inherent in applications. Industrial and prototype implementations have already demonstrated the benefits achieved by CMPs with hundreds of cores.CMP architects are challenged to take many complex design decisions. Only a few of them are:- What should be the ratio between the core and cache areas on a chip?- Which core architectures to select?- How many cache levels should the memory subsystem have?- Which interconnect topologies provide efficient on-chip communication?These and many other aspects create a complex multidimensional space for architectural exploration. Design Automation tools become essential to make the architectural exploration feasible under the hard time-to-market constraints. The exploration methods have to be efficient and scalable to handle future generation on-chip architectures with hundreds or thousands of cores.Furthermore, once a CMP has been fabricated, the need for efficient deployment of the many-core processor arises. Intelligent techniques for task mapping and scheduling onto CMPs are necessary to guarantee the full usage of the benefits brought by the many-core technology. These techniques have to consider the peculiarities of the modern architectures, such as availability of enhanced power saving techniques and presence of complex memory hierarchies.This thesis has several objectives. The first objective is to elaborate the methods for efficient analytical modeling and architectural design space exploration of CMPs. The efficiency is achieved by using analytical models instead of simulation, and replacing the exhaustive exploration with an intelligent search strategy. Additionally, these methods incorporate high-level models for physical planning. The related contributions are described in Chapters 3, 4 and 5 of the document.The second objective of this work is to propose a scalable task mapping algorithm onto general-purpose CMPs with power management techniques, for efficient deployment of many-core systems. This contribution is explained in Chapter 6 of this document.Finally, the third objective of this thesis is to address the issues of the on-chip interconnect design and exploration, by developing a model for simultaneous topology customization and deadlock-free routing in Networks-on-Chip. The developed methodology can be applied to various classes of the on-chip systems, ranging from general-purpose chip multiprocessors to application-specific solutions. Chapter 7 describes the proposed model.The presented methods have been thoroughly tested experimentally and the results are described in this dissertation. At the end of the document several possible directions for the future research are proposed.

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Section: Resultsmentioning

confidence: 99%

Section: Power Modelmentioning

confidence: 99%

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Automatic synthesis and optimization of chip multiprocessors

Nikitin

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Efficient parallel computation of the estimated covariance matrix

Lee

Galperin

Green

et al. 2010

2010 IEEE 26-Th Convention of Electrical and Electronics Engineers in Israel

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Computation of a signal's estimated covariance matrix is an important building block in signal processing, e.g., for spectral estimation. It involves a sliding window over an input matrix, and the summation of products to construct any given output-matrix element. Any given product contributes to multiple output elements, thereby complicating parallelization. We present a novel algorithm that attains very high parallelism without repeating multiplications or requiring inter-core synchronization. Key to this is the assignment to each core of distinct diagonal segments of the output matrix, selected such that no multiplications need be repeated, and exploitation of a shared memory (including L1 cache) that obviates the need for a corresponding awkward partitioning of the memory among cores. Implementation on Plurality's shared memory many-core architecture and, in order to demonstrate additional benefits, also on the x86, reveals linear speedup and a 130-fold power-performance advantage over x86.

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