Performance analysis of multi-dimensional packet classification on programmable network processors

Srinivasan, Deepa; Feng, Wu-chang

doi:10.1016/j.comcom.2004.12.019

Cited by 9 publications

(7 citation statements)

References 13 publications

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“…Rashti et al [8] present a multidimensional packet classifier engine for NP-based firewalls, established on a hierarchical trie algorithm and on a technique of memory usage optimization. Srinivasan and Feng [9] study the performance of two different design mappings of the bit vector algorithm on the Intel IXP1200 NP. Hsu et al [10] propose a bit compression algorithm, also for Intel IXP1200, which requires few memory accesses and allows high performance.…”

Section: Related Workmentioning

confidence: 99%

REFINE: The reconfigurable packet filtering on network processor

Ficara

Giordano

Rossi³

et al. 2008

Int J Communication

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SUMMARYNetwork processors (NPs) are emerging as very promising platforms for developing reconfigurable and high-performance network devices, due to their capability to combine the flexibility of general-purpose processors with the high-performance features of hardware-based systems. They represent the most suitable solutions for implementing complex and dynamic tasks, such as packet classification and scheduling, which are key operations, for example, in DS networks. Programmability and reconfigurability allow NP-based devices to be continuously adapted to the new network requirements, obtaining a high time in market.This paper illustrates the compound process that leads to the implementation of a reconfigurable multidimensional packet filtering on the Intel R IXP2400 NP. The multidimensional multibit trie is chosen as the best algorithm to be implemented and it is modified to exploit the specific features of NP. The different tasks are mapped on the NP computational resources and an optimized implementation is performed, with subsequent experimental validation.

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Section: Related Workmentioning

confidence: 99%

REFINE: The reconfigurable packet filtering on network processor

Ficara

Giordano

Rossi³

et al. 2008

Int J Communication

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“…with more than 10 6 filters) and 2-dimensional searches (such as FIS-tree, Tuple Space Search [15], etc). The problem with all the software approaches is that they cannot support more than 1Gbps rates even when executed on the state-of-the-art network processors [9], [18].…”

Section: Related Workmentioning

confidence: 99%

Memory-Efficient 5D Packet Classification At 40 Gbps

Papaefstathiou

Papaefstathiou²

2007

IEEE INFOCOM 2007 - 26th IEEE International Conference on Computer Communications

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Packet classification is one of the most important enabling technologies for next generation network services. Even though many multi-dimensional classification algorithms have been proposed, most of them are precluded from commercial equipments due to their high memory requirements. In this paper, we present an efficient packet classification scheme, called Bloom Based Packet Classification (B2PC). B2PC comprises of an innovative 5-field search algorithm that decomposes multifield classification rules into internal single field rules which are combined using multi-level Bloom filters. The design of B2PC is optimized for the common case based on analysis of real world classification databases. The hardware implementation of this scheme handles 4K rules by involving only 530KB of memory for its data structures, while it supports network streams at a rate of 15Gbps even in the worst case, and more than 40Gbps in the average case. This system covers 1.3 mm 2 in a 0.18µm CMOS technology. We show that given a certain memory budget and silicon cost, the B2PC is the most efficient hardware-based approach to the classification problem.

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“…Srinivasan and W. Feng implemented the basic BitVector flow classification algorithm on the Intel IXP1200 network processor [23]. They compared parallel mapping and pipelined mapping of the algorithm and showed that parallel mapping has better processing rate.…”

Section: Related Work On Npmentioning

confidence: 99%

Towards high-performance flow-level packet processing on multi-core network processors

et al. 2007

Proceedings of the 3rd ACM/IEEE Symposium on Architecture for Networking and Communications Systems

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There is a growing interest in designing high-performance network devices to perform packet processing at flow level. Applications such as stateful access control, deep inspection and flow-based load balancing all require efficient flow-level packet processing. In this paper, we present a design of high-performance flow-level packet processing system based on multi-core network processors. Main contribution of this paper includes: a) A high performance flow classification algorithm optimized for network processors; b) An efficient flow state management scheme leveraging memory hierarchy to support large number of concurrent flows; c) Two hardware-optimized order-preserving strategies that preserve internal and external per-flow packet order. Experimental results show that: a) The proposed flow classification algorithm, AggreCuts, outperforms the well-known HiCuts algorithm in terms of classification rate and memory usage; b) The presented SigHash scheme can manage over 10M concurrent flow states on the Intel IXP2850 NP with extremely low collision rate; c) The performance of internal packet order-preserving scheme using SRAM queue-array is about 70% of that of external packet orderpreserving scheme realized by ordered-thread execution.

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Performance analysis of multi-dimensional packet classification on programmable network processors

Cited by 9 publications

References 13 publications

REFINE: The reconfigurable packet filtering on network processor

REFINE: The reconfigurable packet filtering on network processor

Memory-Efficient 5D Packet Classification At 40 Gbps

Towards high-performance flow-level packet processing on multi-core network processors

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