Performance analysis of on-chip communication architecture in MPSoC

Optimal Design of Reconfigurable Arbiter Algorithm used in On-Chip S.O.C.

“…We have discussed some of the issues related to the design of S.O.C with regard to the inter process communication of Various bus architectures and protocols have been review [1]. Currently, on-chip communication networks are mostly implemented using shared interconnects like buses [2]. Hence in the future research, it is focused to design an arbiter that dynamically schedules the requests by various masters occurring simultaneously and thus improving the performance of a multiprocessor with respect to latency and bandwidth [3].…”

“…TDMA lend its time with the lowest priority only during idle time. The advantage of this to implement a few execution requests in a particular time [2]. The disadvantage of this misleads of data transfer instead of reserved slots moves to other slots and low bandwidth.…”

An Asynchronous Adaptive Priority Round‐Robin Arbiter Based on Four‐Phase Dual‐rail Protocol

“…T f = T delay /T work (5) where T work is the total work time and T delay is the total idle time [18,19] . In bus-based arbitration, only one master among n masters could get the ownership of bus.…”

An intelligent arbiter for maximum CPU utilization, fair bandwidth allocation and low latency: Survey

“…Since arbiter is an important functional module in multiprocessor, therefore it should be carefully designed in high performance systems [17]. In order to optimize the performance of the bus, the time required to handle the request should be minimized [18,19]. Adaptive arbiter can provide the best bus bandwidth allocation as it distributes different bus bandwidth according to the real-time needs of different masters.…”