Performance analysis of operational transconductance amplifier at 180nm technology

Bendre, Varsha; Kureshi, A. K.

doi:10.1109/cipech.2016.7918781

Cited by 13 publications

(5 citation statements)

References 10 publications

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“…Varsha Bendre et al [10] Presents a performance analysis of two-stage trans-conductance operational amplifier considering conventional gate driven mode using TSMC 180nm technology. From analysis settling time has been 472ns slew rate is achieved 0.37V/ µs, output swing around 1.25V, power dissipation is 536.5 µW, and supply voltage is 1.8V.…”

Section: Literature Surveymentioning

confidence: 99%

A Versatile Design of Low Power and High-Speed Operational Amplifier using Nano Scale Transistors

Asharani*,

Chinnaaiah,

Keerthi

et al. 2020

IJITEE

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This paper illustrates the design of low power and high-speed operational Amplifier using Nanoscale Transistors. The proposed design introduces biasing block, for generating I=10uA for Channel length=180nm Technology. Adding biasing block to two-stages operational Amplifier current is constant i.e. there are no fluctuations in power supply, increase in bandwidth and power dissipation is less as compared the previous result. The design is simulated in p-spice tool and performed AC analysis. After analysis, the design achieved the parameter like Gain = 40db, Phase Margin=90º, Unity Gain Band Width=13MHz, Output Swing=0.1v to 1.7v and Power Dissipation=0.145mW.

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Section: Literature Surveymentioning

confidence: 99%

A Versatile Design of Low Power and High-Speed Operational Amplifier using Nano Scale Transistors

Asharani*,

Chinnaaiah,

Keerthi

et al. 2020

IJITEE

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“…As a result of scaling of transistor's aspect ratios to very deep submicron technology, it becomes harder to accomplish significant op amp gains due to various non-ideal phenomenons and parasitic [1]. In practice different compensation and current mirror techniques are developed to obtain desired performance.…”

Section: Folded Cascode Op Ampmentioning

confidence: 99%

“…The process variations of a device are mainly contributed by various fabrication steps such as oxidation, ion implantation, lithography. This results into considerable variations in the circuit performance and degradation in yields which increases manufacturing expenses [1,7]. Finding ways to minimize the impact of the problem of these variations will remain a major challenge for future technology nodes.…”

Section: A Process Variationsmentioning

confidence: 99%

Design and PVT Analysis of Robust, High Swing Folded Cascode Operational Amplifier

Bendre,

Kureshi

2019

IJEAT

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The folded cascode operational amplifier (FCOA) designed in this paper is the single-pole operational amplifier (op amp). In this design, the conventional current mirror is replaced with wide swing current mirror to overcome the essential drawback of cascode configuration. In this paper, negative feedback is used to improve the small-signal gain and to ensure better stability than multistage amplifiers. This paper also aims at improving the output voltage swing, power dissipation and robustness of the op amp. The designed FCOA is proficient in achieving 67.44dB gain and 1.77V output swingat typical voltage for 180nm CMOS technology. The FCOA is highly stable with phase margin of 62.58º while dissipating 0.5mW power. This amplifier is further verified for variability analysis for Process, Voltage and Temperature (PVT) variations to check robustness. All together testing is done at 45 different PVT combinations and results are tabulated accordingly. At each corner temperature and voltage are varied for all together nine combinations to properly address the effect of PVT variations. The results shows that the op amp exhibits desired response at four corners (FF, TT, SS, and FS) of process, over -40º to 125º C temperature range. Also it is capable of operating at very low voltage up to 0.9V adequately showing reduction in power dissipation. Thus the designed op amp is low power, high swing and robust towards process, voltage and temperature variations.

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“…In those systems, the threshold voltages ( ) of the MOSFETs are not reducing compared to the rate at which the power supplies voltages reduction [4] and the ratio of lengths-to-widths of the down-scaled MOSFETs channels [5]. In very LVs power supplies and LP MOSFETs circuits, the minimum power supplies voltages must be equal to or greater than the values, and this imposes an additional strict restriction on the possibility of reducing the power supplies voltages [6].…”

Section: Introductionmentioning

confidence: 99%

“…However, Digital MOSFETs circuits benefit from the use of low-values MOSFETs and very LVs power supplies to improve their performance specifications. Whereas, the use of low-values MOSFETs and very LVs power supplies lead to the deterioration in the performance specifications of the analog MOSFETs circuits due to the effects of gate leakage currents, short-channel lengths, and permissible noise voltages margins [4][5][6][7][8][9]. Consequently, these effects increase the complexity of designing the analog…”

Section: Introductionmentioning

confidence: 99%

Design of very low-voltages and high-performance CMOS gate-driven operational amplifier

AL-Qaysi

Jasim

Hameed

2020

IJEECS

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This paper presents the description and analysis of the design and HSPICE-based simulation results of very low-voltages (LVs) power supplies and high-performance specifications CMOS gate-driven (GD) operational amplifier (Op-Amp) circuit. The very LVs CMOS GD Op-Amp circuit designed using 90nm CMOS technology parameters and the folded cascode (FC) technique employed in the differential input stage. The HSPICE simulation results demonstrate that the overall gain is 73.1dB, the unity gain bandwidth is 14.9MHz, the phase margin is , the total power dissipation is 0.91mW, the output voltage swing is from 0.95V to 1V, the common-mode rejection ratio is dB, the equivalent input-referred noise voltage is 50.94 at 1MHz, the positive slew rate is 11.37 , the negative slew rate is 11.39 , the settling time is 137 , the positive power-supply rejection ratio is 74.2dB, and the negative power-supply rejection ratio is 80.1dB. The comparisons of simulation results at 1V and 0.814V power supplies’ voltages of the very LVs CMOS GD Op-Amp circuit demonstrate that the circuit functions with perfect performance specifications, and it is suitable for many considerable applications intended for very LVs CMOS Op-Amp circuits.

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Performance analysis of operational transconductance amplifier at 180nm technology

Cited by 13 publications

References 10 publications

A Versatile Design of Low Power and High-Speed Operational Amplifier using Nano Scale Transistors

A Versatile Design of Low Power and High-Speed Operational Amplifier using Nano Scale Transistors

Design and PVT Analysis of Robust, High Swing Folded Cascode Operational Amplifier

Design of very low-voltages and high-performance CMOS gate-driven operational amplifier

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