Performance analysis of pre-equalized multilevel partial response modulation for high-speed electrical interconnects

IEEE Trans. Wireless Commun.

Guenach

et al. 2020

Due to the continuous demand for higher bit rates, the management of the spatio-temporal intersymbol interference in frequency-selective multiple-input multiple-output (MIMO) channels becomes increasingly important. For single-input singleoutput channels, equalized precoded partial-response signaling is capable of handling a large amount of intersymbol interference, but, to date, no equalization scheme with general partial-response signaling has been presented for the frequency-selective MIMO channel. Not only does this contribution extend partial-response signaling to the MIMO channel by proposing a general spatiotemporal partial-response precoder, but it also develops a minimum mean-squared-error optimization framework in which the equalization coefficients and the spatio-temporal target response are jointly optimized. Three iterative optimization algorithms are discussed, which update (part of) a row of the target impulse response matrix in each iteration. In particular, the third algorithm reformulates this row optimization as a lattice decoding problem. Numerical simulations confirm that the general partial-response signaling clearly outperforms the traditional full-response signaling in terms of the mean squared error and the bit error rate. The third optimization algorithm has a better performance but a higher complexity, compared to the first and the second algorithm.

Section: Ber Expression For Prsmentioning

confidence: 67%

Optimized Precoded Spatio-Temporal Partial-Response Signaling Over Frequency-Selective MIMO Channels

IEEE Trans. Wireless Commun.

Guenach

et al. 2020

“…In this contribution, we tackle the latency issue by setting to zero the first N taps of the feedback filters of a MIMO DFE scheme consisting of a fixed pre-equalizer at the TX and adjustable feedforward and feedback filters at the RX. Moreover, the resulting scheme is combined with partial response (PR) signaling, which has been shown to improve the performance of high-speed serial links because it allows some controlled residual ISI and, hence, reduces the required equalization effort [8], [9]. We derive neat matrix expressons for the minimum meansquare error (MMSE) equalization filters and show how precoded PR signaling on a specific 4×4 chip-tochip interconnect can enhance the error performance of MIMO DFE.…”

Section: Introductionmentioning

confidence: 99%

On Partial Response Signaling for MIMO Equalization on Multi-Gbit/s Electrical Interconnects

2018 26th European Signal Processing Conference (EUSIPCO)

Manfredi

et al. 2018

Because of its ability to deal with intersymbol interference (ISI) and crosstalk (XT) over mutually coupled electrical interconnects, multiple-input multipleoutput (MIMO) decision feedback equalization (DFE) has proven to be a promising low-cost solution for achieving multi-Gbit/s wireline communication on-and off-chip. However, not only does the channel become very sensitive to manufacturing tolerances at very high symbol rates, the latency in the feedback loop becomes prohibitively large as well. Whereas the former issue has been addressed by adopting a stochastic MIMO approach where (part of) the equalization filters depend on the channel statistics rather than on the actual channel, we tackle in this paper the latency issue by setting to zero the first N taps of the feedback filters. Moreover, we show that precoded partial response (PR) signaling can improve the performance of the resulting scheme, although the achieved gain is smaller than in the case of single-input single-output (SISO) equalization.

“…Furthermore, the fully adjustable equalization schemes maintain a nearly constant average MSE irrespective of the level of variability, and largely outperform the fixed and hybrid schemes when the variability is very high. The corresponding average BERs, obtained using the semianalytical method from [10], are shown in Fig. 4.…”

Section: Hybrid Equalization Schemementioning

confidence: 99%

MIMO Equalization for Multi-Gbit/s Access Nodes Affected by Manufacturing Tolerances

GLOBECOM 2017 - 2017 IEEE Global Communications Conference

Manfredi

et al. 2017

Self Cite

Abstract-While the requirements for delivering high throughputs increase exponentially with every generation of access node hardware, the device cost is of primary concern. As a result, multiple-input multipleoutput (MIMO) equalization, which has been shown to facilitate multi-Gbit/s communication over low-cost parallel electrical interconnects, is emerging as an attractive high-speed interconnect solution for next-generation access nodes. Because of the high operating frequencies, however, the transfer functions of the on-and off-chip interconnects become highly susceptible to manufacturing tolerances (MTs); hence, the equalization filters must be adjusted to the specific channel realization to achieve optimal performance, which involves a high implementation and computational complexity. Considering that the MTs are usually limited, we propose a robust lowcomplexity transceiver consisting of a fixed MIMO linear pre-equalizer (which avoids the need for feeding back the channel state information to the transmitter), with either a fixed or adjustable MIMO decision-feedback equalizer (DFE). For a specific chip-to-chip interconnect operating at 75 Gbit/s per line and a 26 dB signal-to-noise ratio, we show that the resulting bit error rate does not exceed 10 −12 for MTs up to 10.5% (fixed DFE) and 17.7% (adjustable DFE) of the nominal line width.