Performance analysis of the Kahan‐enhanced scalar product on current multi‐core and many‐core processors

Hofmann, Jan; Fey, Dietmar; Riedmann, M.; Eitzinger, Jan; Hager, Georg; Wellein, Gerhard

doi:10.1002/cpe.3921

Cited by 6 publications

(10 citation statements)

References 22 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A full introduction to the ECM model would exceed the scope of this paper, so we refer to the references given above. The model has been shown to work well for the analysis of implementations of several important computational kernels [19,18,23,2,9].…”

Section: Performance On Modern Multicore Cpusmentioning

confidence: 99%

“…Instead, time contributions from in-core execution and data transfers through the memory hierarchy are calculated and then put together according to the properties of a particular processor architecture; for instance, in Intel x86 server CPUs all time contributions from data transfers including LOADs and STOREs in the L1 cache must be added to get a prediction of single-core data transfer time [18,8]. On the other hand, the IBM Power8 processor shows almost perfect overlap [9]. A full introduction to the ECM model would exceed the scope of this paper, so we refer to the references given above.…”

Section: Performance On Modern Multicore Cpusmentioning

confidence: 99%

“…Modeling the memory hierarchy in the ECM model requires the maximum data bandwidth between adjacent cache levels (assuming that the hierarchy is inclusive) and the maximum (saturated) memory bandwidth. As for the caches it is usually sufficient to assume the maximum documented theoretical bandwidth (presupposing that all prefetchers work perfectly to hide latencies), although latency penalties might apply [9]. The main memory bandwidth and latency may depend on the cluster-on-die (CoD) mode and cache snoop mode settings.…”

Section: Performance On Modern Multicore Cpusmentioning

confidence: 99%

See 2 more Smart Citations

An Analysis of Core- and Chip-Level Architectural Features in Four Generations of Intel Server Processors

Hofmann

Hager

Wellein

et al. 2017

Lecture Notes in Computer Science

Self Cite

View full text Add to dashboard Cite

Abstract. This paper presents a survey of architectural features among four generations of Intel server processors (Sandy Bridge, Ivy Bridge, Haswell, and Broadwell) with a focus on performance with floating point workloads. Starting on the core level and going down the memory hierarchy we cover instruction throughput for floating-point instructions, L1 cache, address generation capabilities, core clock speed and its limitations, L2 and L3 cache bandwidth and latency, the impact of Cluster on Die (CoD) and cache snoop modes, and the Uncore clock speed. Using microbenchmarks we study the influence of these factors on code performance. This insight can then serve as input for analytic performance models. We show that the energy efficiency of the LINPACK and HPCG benchmarks can be improved considerably by tuning the Uncore clock speed without sacrificing performance, and that the Graph500 benchmark performance may profit from a suitable choice of cache snoop mode settings.

show abstract

Section: Performance On Modern Multicore Cpusmentioning

confidence: 99%

Section: Performance On Modern Multicore Cpusmentioning

confidence: 99%

Section: Performance On Modern Multicore Cpusmentioning

confidence: 99%

See 1 more Smart Citation

An Analysis of Core- and Chip-Level Architectural Features in Four Generations of Intel Server Processors

Hofmann

Hager

Wellein

et al. 2017

Lecture Notes in Computer Science

Self Cite

View full text Add to dashboard Cite

show abstract

“…the single-core model, are presented here. Readers interested in the full ECM model can find the most recent version for Intel Xeon, Intel Xeon Phi, and IBM POWER8 processors here [6].…”

Section: The Ecm Performance Modelmentioning

confidence: 99%

An ECM-based Energy-Efficiency Optimization Approach for Bandwidth-Limited Streaming Kernels on Recent Intel Xeon Processors

Hofmann

Fey

2016

2016 4th International Workshop on Energy Efficient Supercomputing (E2SC)

Self Cite

View full text Add to dashboard Cite

We investigate an approach that uses low-level analysis and the execution-cache-memory (ECM) performance model in combination with tuning of hardware parameters to lower energy requirements of memory-bound applications. The ECM model is extended appropriately to deal with software optimizations such as nontemporal stores. Using incremental steps and the ECM model, we analytically quantify the impact of various single-core optimizations and pinpoint microarchitectural improvements that are relevant to energy consumption. Using a 2D Jacobi solver as example that can serve as a blueprint for other memory-bound applications, we evaluate our approach on the four most recent Intel Xeon E5 processors (Sandy Bridge-EP, Ivy Bridge-EP, Haswell-EP, and Broadwell-EP). We find that chip energy consumption can be reduced in the range of 2.0-2.4× on the examined processors.

show abstract

“…Paper investigates the performance characteristics of a numerically enhanced scalar product kernel loop that uses the Kahan algorithm to compensate for numerical errors. By applying the model‐guided performance engineering, the author's approach enables the system to detect the relevant performance bottlenecks for single‐core and thread‐parallel executions and to predict performance and saturation behavior.…”

mentioning

confidence: 99%

Algorithmic advances for parallel architectures

Wyrzykowski

Szymański

2017

Concurrency and Computation

View full text Add to dashboard Cite

This special issue of Concurrency and Computation: Practice and Experience contains revised and extended versions of selected papers presented at the 11th International Conference on Parallel Processing and Applied Mathematics, PPAM 2015, which was held on September 6 to 9, 2015, in Krakow, Poland.PPAM is a biennial series of international conferences dedicated to exchanging ideas between researchers involved in parallel and distributed computing, including theory and applications, as well as applied and computational mathematics. The focus of PPAM 2015 was on models, algorithms, and software tools that facilitate efficient and convenient use of modern parallel and distributed computing systems, as well as on large-scale applications, including data-intensive problems. This meeting gathered more than 190 participants from 33 countries. A strict reviewing process, with each submission reviewed at least three times, resulted in acceptance of 111 contributed papers with the acceptance rate of 57%. The accepted papers were presented at the regular tracks of the PPAM 2015 conference, as well as during the workshops that were important and integral parts of the PPAM 2015 meeting.Based on the results of the reviews, selected papers were recommended for a special journal issue. Besides quality, another important goal that influenced the paper selection was a maximum possible thematic consistency of the issue. The focus of this special issue is on algorithmic advances to better match the software properties to the targeted parallel architecture. These advances vary from general, like increasing potential reuse of a part of computation, to specific for a particular architecture, eg, using GPUs or with multi-core and many-core processors, or specific applications, such as spherical Delaunay triangulations, or visualization of complex networks. The authors were contacted after the conference and invited to submit revised and extended versions of their papers. These new versions were reviewed independently by three reviewers. Finally, nine contributions were accepted for publication. They are summarized below.Paper [1] focuses on LU factorization, which is a recurrent operation in scientific and engineering applications used to solve linear systems. In particular, the authors adapt the Gauss-Huard algorithm that has been introduced as an efficient solution for modern platforms equipped with accelerators to improve reusing of computations in this algorithm. This approach was evaluated on the solution of Lyapunov matrix equations via the LRCF-ADI method and validated on three benchmarks. In future work, the authors plan to design a heuristic for choosing the optimal block size and to integrate their solution with the mixed precision techniques to further accelerate the Lyapunov solver.An efficient algorithm for solving dense symmetric indefinite systems on GPUs is presented in the work of Baboulin et al. [2]. The critical challenge on these types of computations on hybrid CPU/GPU is to keep to minimum the expensive data transf...

show abstract

Performance analysis of the Kahan‐enhanced scalar product on current multi‐core and many‐core processors

Cited by 6 publications

References 22 publications

An Analysis of Core- and Chip-Level Architectural Features in Four Generations of Intel Server Processors

An Analysis of Core- and Chip-Level Architectural Features in Four Generations of Intel Server Processors

An ECM-based Energy-Efficiency Optimization Approach for Bandwidth-Limited Streaming Kernels on Recent Intel Xeon Processors

Algorithmic advances for parallel architectures

Contact Info

Product

Resources

About