Performance and energy consumption of HPC workloads on a cluster based on Arm ThunderX2 CPU

Mantovani, Filippo; García-Gasulla, Marta; Gracia, José Luis Pano; Stafford, Esteban; Banchelli, Fabio; Josep-Fabrego, Marc; Criado-Ledesma, Joel; Nachtmann, Mathias

doi:10.1016/j.future.2020.06.033

Cited by 27 publications

(7 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…After Linpack, the most popular benchmarks in the HPC community target specific architecture features: HPCG [11], NAS parallel benchmarks [4] or IO500 [24]. For the purpose of evaluating new architectures, these benchmarks are too specific [22], which calls for a bottom up approach. This means developing benchmarks, kernels and micro-applications that mimic some of the features or phases of scientific workloads: CORAL [2], Graph500 [25].…”

Section: Related Workmentioning

confidence: 99%

Size & Shape Matters: The Need of HPC Benchmarks of High Resolution Image Training for Deep Learning

Pont

Megias

Garcia-Gasulla

et al. 2021

JSFI

View full text Add to dashboard Cite

One of the purposes of HPC benchmarks is to identify limitations and bottlenecks in hardware. This functionality is particularly influential when assessing performance on emerging tasks, the nature and requirements of which may not yet be fully understood. In this setting, a proper benchmark can steer the design of next generation hardware by properly identifying said requirements, and quicken the deployment of novel solutions. With the increasing popularity of deep learning workloads, benchmarks for this family of tasks have been gaining popularity. Particularly for image based tasks, which rely on the most well established family of deep learning models: Convolutional Neural Networks. Significantly, most benchmarks for CNN use low-resolution and fixed-shape (LR&FS) images. While this sort of inputs have been very successful for certain purposes, they are insufficient for some domains of special interest (e.g., medical image diagnosis or autonomous driving) where one requires higher resolutions and variable-shape (HR&VS) images to avoid loss of information and deformation. As of today, it is still unclear how does image resolution and shape variability affect the nature of the problem from a computational perspective. In this paper we assess the differences between training with LR&FS and HR&VS, as means to justify the importance of building benchmarks specific for the latter. Our results on three different HPC clusters show significant variations in time, resources and memory management, highlighting the differences between LR&FS and HR&VS image deep learning.

show abstract

Section: Related Workmentioning

confidence: 99%

Size & Shape Matters: The Need of HPC Benchmarks of High Resolution Image Training for Deep Learning

Pont

Megias

Garcia-Gasulla

et al. 2021

JSFI

View full text Add to dashboard Cite

show abstract

“…[4] and ThunderX2 [34]. Table 1 lists the specification of the hardware platforms used in our evaluation.…”

Section: Work Partitioningmentioning

confidence: 99%

“…Results. We demonstrate the benefit of LibShalom by applying it to three representative ARMv8 multi-core CPUs, Phytium 2000+ [16], Kunpeng 920 [4] and ThunderX2 [34]. We evaluate LibShalom on both small and irregular-shaped GEMMs as well as computation kernels from real-life applications.…”

Section: Introductionmentioning

confidence: 99%

Libshalom

Yang

Fang

Dong

et al. 2021

Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis

View full text Add to dashboard Cite

General Matrix Multiplication (GEMM) is a key subroutine in highperformance computing. While the mainstream linear algebra libraries can deliver high performance on large and regular-shaped GEMM, they are inadequate for optimizing small and irregularshaped GEMMs, which are commonly seen in new HPC applications. Some of the recent works in this direction have made promising progress on x86 architectures and GPUs but still leave much room for improvement on emerging HPC hardware built upon the ARMv8 architecture. We present LibShalom, an open-source library for optimizing small and irregular-shaped GEMMs, explicitly targeting the ARMv8 architecture. LibShalom builds upon the classical Goto algorithm but tailors it to minimize the expensive memory accessing overhead for data packing and processing small matrices. It uses analytic methods to determine GEMM kernel optimization parameters, enhancing the computation and parallelization efficiency of the GEMM kernels. We evaluate LibShalom by applying it to three ARMv8 multi-core architectures and comparing it against five mainstream linear algebra libraries. Experimental results show that LibShalom can consistently outperform existing solutions across GEMM workloads and hardware architectures. CCS CONCEPTS• Computer systems organization; • Software and its engineering → Compilers;

show abstract

“…Dibona is an Armbased experimental cluster based on the Bull/ATOS Sequana infrastructure with compute nodes powered by two Marvell ThunderX2 CN9980 processors, each with 32 Armv8 cores. More details about the Dibona cluster can be found in [19], [20]. Table I shows the details of the hardware configurations of the two platforms.…”

Section: B Hardware Environmentmentioning

confidence: 99%

CoreNEURON: Performance and Energy Efficiency Evaluation on Intel and Arm CPUs

Criado

García-Gasulla

Kumbhar

et al. 2020

2020 IEEE International Conference on Cluster Computing (CLUSTER)

Self Cite

View full text Add to dashboard Cite

model of a rat hippocampus CA1 1. This model has about 447 thousand neurons, 304 million compartments, and 990 million synapses. To study such models at different scales, the community has developed various simulation software such as NEURON [1] for morphologically detailed neuron models, NEST [2] for point neuron models, and STEPS [3] for simulations at the molecular level. The simulation of morphologically detailed neuronal circuits like rat hippocampus CA1 is computationally expensive and requires access to a large computing cluster. Analyzing and optimizing such simulation software's performance on different hardware platforms is essential for delivering scientific results faster, and reducing the computational cost of such large scale simulations. In this paper, we present our efforts to analyze the performance of CoreNEURON [4], a compute engine of widely used NEURON simulator. Specifically, by using newly developed NMODL source to source compiler framework [5] with ISPC backend [6], we analyzed different performance metrics to evaluate Intel and Arm platforms. For decades scientific computing has been associated with mostly a single architecture, Intel x86. Since November 2018, the Armv8 architecture is part of the Top500 list 2 with the Astra supercomputer [7]. In June 2020, Fugaku by Fujitsu powered by the Arm Instruction Set Architecture (ISA), has been ranked as the fastest supercomputer in the world. Therefore, a valid question is how well complex applications such as neural simulations behave on high-performance systems powered by different architectures? There are several approaches in the literature [8], [9], mostly targeting Arm mobile SoCs. We employ server-grade Arm CPUs similar to [10], [11], but evaluating a different workflow. We isolated three layers that can affect the performance

show abstract

Performance and energy consumption of HPC workloads on a cluster based on Arm ThunderX2 CPU

Cited by 27 publications

References 10 publications

Size & Shape Matters: The Need of HPC Benchmarks of High Resolution Image Training for Deep Learning

Size & Shape Matters: The Need of HPC Benchmarks of High Resolution Image Training for Deep Learning

Libshalom

CoreNEURON: Performance and Energy Efficiency Evaluation on Intel and Arm CPUs

Contact Info

Product

Resources

About