Performance and power of cache-based reconfigurable computing

Putnam, Andrew; Eggers, Susan J.; Bennett, Dave; Dellinger, Eric; Mason, Jeff; Styles, Henry; Sundararajan, Prasanna; Wittig, Ralph

doi:10.1145/1508128.1508189

Cited by 11 publications

(12 citation statements)

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“…Compiling C code to hardware targeting a CPU-FPGA architecture is also addressed in the CHiMPS framework [64]. The idea is similar in that it generates a parallel on-chip multicache (many-cache) architecture in order to feed parallel data paths.…”

Section: Profiling and User Annotation-based Approachesmentioning

confidence: 99%

“…The goal in this work is di↵erent: we infer cost/performance estimates prior to implementation and devise an automated cache system construction for a given application instead of exploring the cache micro-architecture. Automatic cache sizing from high-level specifications has been addressed in [67,64]. Wingbermuehle et al [67] implement a method similar to ours in that left-over memory resources are used to enhance the memory sub-system of stream-based kernels.…”

Section: Profiling and User Annotation-based Approachesmentioning

confidence: 99%

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Separation Logic for High-level Synthesis

Winterstein¹

2017

Springer Theses

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High-level synthesis (HLS) promises a significant shortening of the FPGA design cycle by raising the abstraction level of the design entry to high-level languages such as C/C++. However, applications using dynamic, pointer-based data structures and dynamic memory allocation remain difficult to implement well, yet such constructs are widely used in software. Automated optimizations that leverage the memory bandwidth of FPGAs by distributing the application data over separate banks of on-chip memory are often ineffective in the presence of dynamic data structures, due to the lack of an automated analysis of pointer-based memory accesses. In this work, we take a step towards closing this gap. We present a static analysis for pointer-manipulating programs which automatically splits heap-allocated data structures into disjoint, independent regions. The analysis leverages recent advances in separation logic, a theoretical framework for reasoning about heap-allocated data which has been successfully applied in recent software verification tools. Our algorithm focuses on dynamic data structures accessed in loops and is accompanied by automated source-to-source transformations which enable automatic loop parallelization and memory partitioning by off-the-shelf HLS tools. We demonstrate the successful loop parallelization and memory partitioning by our tool flow using three real-life applications which build, traverse, update and dispose dynamically allocated data structures. Our case studies, comparing the automatically parallelized to the direct HLS implementations, show an average latency reduction by a factor of 2× across our benchmarks.

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Section: Profiling and User Annotation-based Approachesmentioning

confidence: 99%

Section: Profiling and User Annotation-based Approachesmentioning

confidence: 99%

Separation Logic for High-level Synthesis

Winterstein¹

2017

Springer Theses

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“…In such a system, our work could be used to discover the best use of the on-chip memory resources to improve performance. Likewise, our system could be used to find more suitable memory subsystems in high-level synthesis tools such as CHiMPS [24] and ScalaPipe [32].…”

Section: Related Workmentioning

confidence: 99%

Superoptimization of memory subsystems

2014

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The disparity in performance between processors and main memories has led computer architects to incorporate large cache hierarchies in modern computers. Because these cache hierarchies are designed to be general-purpose, they may not provide the best possible performance for a given application. In this paper, we determine a memory subsystem well suited for a given application and main memory by discovering a memory subsystem comprised of caches, scratchpads, and other components that are combined to provide better performance. We draw motivation from the superoptimization of instruction sequences, which successfully finds unusually clever instruction sequences for programs. Targeting both ASIC and FPGA devices, we show that it is possible to discover unusual memory subsystems that provide performance improvements over a typical memory subsystem.

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“…ECOcores provide a higher-performing and moreefficient memory system, with pipelined access and integrated cachelets. The CHiMPS multi-cache architecture [23] uses several application-specific caches and enforces coherence via flushing, but the purpose, sizing, and implementation of CHiMPS multi-cache differs from the cachelet approach. CHiMPS aggregates 4-KB block RAMs on an FPGA into caches backing different regions of memory in order to provide memory parallelism and to simplify the memory interface for a C-like programming model.…”

Section: Related Workmentioning

confidence: 99%

Efficient complex operators for irregular codes

Sampson

Venkatesh

Goulding-Hotta

et al. 2011

2011 IEEE 17th International Symposium on High Performance Computer Architecture

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Complex "fat operators" are important contributors to the efficiency of specialized hardware. This paper introduces two new techniques for constructing efficient fat operators featuring up to dozens of operations with arbitrary and irregular data and memory dependencies. These techniques focus on minimizing critical path length and loaduse delay, which are key concerns for irregular computations. Selective Depipelining(SDP) is a pipelining technique that allows fat operators containing several, possibly dependent, memory operations. SDP allows memory requests to operate at a faster clock rate than the datapath, saving power in the datapath and improving memory performance. Cachelets are small, customized, distributed L0 caches embedded in the datapath to reduce load-use latency. We apply these techniques to Conservation Cores(ccores) to produce coprocessors that accelerate irregular code regions while still providing superior energy efficiency. On average, these enhanced c-cores reduce EDP by 2× and area by 35% relative to c-cores. They are up to 2.5× faster than a general-purpose processor and reduce energy consumption by up to 8× for a variety of irregular applications including several SPECINT benchmarks. Recent work [27] examined one approach to improving the energy efficiency of these codes by converting dark silicon into a collection of energy-saving applicationspecialized cores called Conservation Cores, or c-cores. That approach emphasized energy savings while matching the performance of a conventional processor, but three factors limited its performance and energy efficiency gains. First, synchronization with the memory system restricted

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Performance and power of cache-based reconfigurable computing

Cited by 11 publications

References 0 publications

Separation Logic for High-level Synthesis

Separation Logic for High-level Synthesis

Superoptimization of memory subsystems

Efficient complex operators for irregular codes

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