Performance and Process Comparison between Glass and Si Interposer for 3D-IC Integration

Abstract

Nowadays, silicon is a mature material in semiconductor technology, but glass, a dielectric material, provides an attractive option due to its intrinsic characteristics for the advantages of electrical isolation, better RF performance, better feasibility with CTE and most importantly low cost solution. In this investigation, the glass interposer by using TSV industry equipment and tooling was evaluated and developed, and has been compared in complete processes and electrical/thermal characteristics with silicon interposer. In order to simulate and measure the electrical/thermal performance, patterned interposer wafer with 30μm diameter and 100μm depth Cu-filled TSVs are designed and prepared in advance. Key technologies include via fabrication, topside RDL formation, micro-bumping, temporary bonding, silicon and glass thinning and backside RDL formation were well developed and integrated to perform for comparison. 30μm via, 60μm pitch, RDL line/space 20μm/30um, 100μm thin wafer/glass and 15um micro-bumping been successfully integrated in the integration platform. The glass interposer was characterized and assessed to have excellent electrical performance and is potentially to be applied for 3D product applications.

3D including 3DIC and 3D Packaging (POP)

“…As a semiconducting material, standard silicon tends to have increased loss at higher frequencies. Work done in collaboration with the Industrial Technology Research Institute (ITRI) in Taiwan illustrates this well [14]. In this work co-planar waveguides (CPW), micro-strip lines (MS) and co-planar waveguides with 2 vias were constructed on glass and silicon substrates, and impedance matched to ~50 ohm.…”

75‐2: Failure Mechanisms and Optimum Methods for Through Glass Via

“…1 The advantages of glass as a promising substrate material for 2.5D and 3D packaging of RF ICs at high performance and low cost have been widely reported. [2][3][4] The vertical electrical feed-through in glass substrate plays a key role in the advanced package, which is based on through glass via (TGV) technology and Cu plating process. 5 The metallized TGV can be used to realize the connection of multilayer redistribution layers (RDL) on the front and back surface for system in package (SiP) and chiplet, especially interposer and 3D stack.…”

Thermo-Mechanical Reliability Study of Through Glass Vias in 3D Interconnection

“…Early studies on glass focused on demonstrating the effects of various copper plating processes on high-frequency transmission characteristics of TGV coplanar waveguides (CPW) and verifying the electrical properties utilizing a daisy chain arrangement. The junction temperature test also shows that the glass interposer provide thermal coupling thermal coupling between chips and can be widely used in 3D products [ 4 ]. These works are filled with TGV blind via plating.…”