Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs

BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers

“…The top two contributors to the static power consumption are the buffers and the crossbar, but the majority of the static power is clearly consumed by the buffers. Such results are aligned with RTL results presented in [14], which considered a router implemented at 65 nm. This quantitative analysis motivates the focus of BlackOut on minimizing the static power consumption of the NoC buffers.…”

“…As part of BlackOut's comprehensive evaluation, this work compares the proposed methodology with two current stateof-the-art power-gating mechanisms, (1) Power Punch [7], and (2) the technique in [14]. The Power Punch mechanism [7] represents the state-of-the-art in coarse-grain power gating (i.e., powering off the entire router), while the mechanism in [14] represents the state-of-the-art in fine-grain power-gating at the buffer-level.…”

“…The Power Punch mechanism [7] represents the state-of-the-art in coarse-grain power gating (i.e., powering off the entire router), while the mechanism in [14] represents the state-of-the-art in fine-grain power-gating at the buffer-level. The experimental results -obtained using both synthetic traffic and real applications -demonstrate that BlackOut substantially outperforms both existing state-of-theart techniques.…”

“…Ultra-fine-grained run-time power gating [14] discusses a power-gating methodology considering a NoC with only a single VC per VNET. Different parts of the same router can be dynamically power-gated to reduce leakage power.…”

“…It organizes the router in micro power domains that can be independently power-gated: buffers, VA, crossbar, and output latches. A critical contribution of [14] is the complete RTL design at 65 nm. In particular, the wakeup time for a 128-bit 4-slot buffer is estimated to be 2.8 ns.…”