Performance-Centric Optimization for Racetrack Memory Based Register File on GPUs

Liang, Yun; Wang, Shuo

doi:10.1007/s11390-016-1610-1

Cited by 10 publications

(6 citation statements)

References 19 publications

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“…This vertical arrangement is considered as a breakthrough, where a forest of such nanowires is arranged, which tremendously increases the storage capacity in RM. Such an arrangement of RM with large data storage capacity and minimum footprint is advocated to replace the current memory structures at different levels such as SRAM and DRAM cache [220,[227][228][229][230][231][232], GPU register [233][234][235], and off-chip (stand-alone) memory [236] owing to its non-volatility, high read/write speed, and lower read/write energy. Diligent efforts needed to investigate the feasibility of replacing the main memory by RM.…”

Section: Magnetic Domain Wall Nanowirementioning

confidence: 99%

Spintronic devices: a promising alternative to CMOS devices

2021

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The field of spintronics has attracted tremendous attention recently owing to its ability to offer a solution for the present-day problem of increased power dissipation in electronic circuits while scaling down the technology. Spintronic-based structures utilize electron’s spin degree of freedom, which makes it unique with zero standby leakage, low power consumption, infinite endurance, a good read and write performance, nonvolatile nature, and easy 3D integration capability with the present-day electronic circuits based on CMOS technology. All these advantages have catapulted the aggressive research activities to employ spintronic devices in memory units and also revamped the concept of processing-in-memory architecture for the future. This review article explores the essential milestones in the evolutionary field of spintronics. It includes various physical phenomena such as the giant magnetoresistance effect, tunnel magnetoresistance effect, spin-transfer torque, spin Hall effect, voltage-controlled magnetic anisotropy effect, and current-induced domain wall/skyrmions motion. Further, various spintronic devices such as spin valves, magnetic tunnel junctions, domain wall-based race track memory, all spin logic devices, and recently buzzing skyrmions and hybrid magnetic/silicon-based devices are discussed. A detailed description of various switching mechanisms to write the information in these spintronic devices is also reviewed. An overview of hybrid magnetic /silicon-based devices that have the capability to be used for processing-in-memory (logic-in-memory) architecture in the immediate future is described in the end. In this article, we have attempted to introduce a brief history, current status, and future prospectus of the spintronics field for a novice.

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Section: Magnetic Domain Wall Nanowirementioning

confidence: 99%

Spintronic devices: a promising alternative to CMOS devices

2021

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“…The immense storage requirement of GPU applications makes RTMs a preferable alternative to be employed as a GPU register file. To this end, various proposals propose RTM-based GPU register files to alleviate the high leakage and scalability problems of conventional SRAMbased register files [86]- [89]. These proposals are based on the tenet of reducing the shift overhead via different techniques that include smart register renaming [86], [87], [89], proactive preshifting [87]- [90], and intelligent thread scheduling [86].…”

Section: B Rtm Gpu Register Filementioning

confidence: 99%

Magnetic Racetrack Memory: From Physics to the Cusp of Applications Within a Decade

et al. 2020

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| Racetrack memory (RTM) is a novel spintronic memory-storage technology that has the potential to overcome fundamental constraints of existing memory and storage devices. It is unique in that its core differentiating feature is the movement of data, which is composed of magnetic domain walls (DWs), by short current pulses. This enables more data to be stored per unit area compared to any other current technologies. On the one hand, RTM has the potential for mass data storage with unlimited endurance using considerably less energy than today's technologies. On the other hand, RTM promises an ultrafast nonvolatile memory competitive with static random access memory (SRAM) but with a much smaller footprint. During the last decade, the discovery of novel physical mechanisms to operate RTM has led to a major enhancement in the efficiency with which nanoscopic, chiral DWs can be manipulated. New materials and artificially atomically engineered thin-film structures have been found to increase the speed and lower the threshold current with which the data bits can be manipulated. With these recent Manuscript

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“…line 18), when the vertex-to-group weight of the selected vertex is equal with both sub-groups, the algorithm compares the edge weight of the selected vertex v * with the last vertices of both groups (v p in д r and v q in д l ) and favors the maximum edge weight (cf. lines [19][20][21][22][23][24].…”

Section: The Shiftsreduce Heuristicmentioning

confidence: 99%

“…While most of these solutions effectively improve both performance and energy, their applicability to RMs is of secondary interests (hybrid RM-S/DRAM memory system). Fundamentally, the data-placement solutions in RMs such as for GPU register files [24], scratchpad memories [13,29], and stacks [14] aim at reducing the number of RM shifts.…”

Section: Related Workmentioning

confidence: 99%

ShiftsReduce

Khan

Hameed

Blaesing

et al. 2019

ACM Trans. Archit. Code Optim.

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Racetrack memories (RMs) have significantly evolved since their conception in 2008, making them a serious contender in the field of emerging memory technologies. Despite key technological advancements, the access latency and energy consumption of an RM-based system are still highly influenced by the number of shift operations. These operations are required to move bits to the right positions in the racetracks. This article presents data-placement techniques for RMs that maximize the likelihood that consecutive references access nearby memory locations at runtime, thereby minimizing the number of shifts. We present an integer linear programming (ILP) formulation for optimal data placement in RMs, and we revisit existing offset assignment heuristics, originally proposed for random-access memories. We introduce a novel heuristic tailored to a realistic RM and combine it with a genetic search to further improve the solution. We show a reduction in the number of shifts of up to 52.5%, outperforming the state of the art by up to 16.1%. CCS Concepts: • Mathematics of computing → Combinatorial optimization; • Hardware → Emerging technologies; • Software and its engineering → Compilers;

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Performance-Centric Optimization for Racetrack Memory Based Register File on GPUs

Cited by 10 publications

References 19 publications

Spintronic devices: a promising alternative to CMOS devices

Spintronic devices: a promising alternative to CMOS devices

Magnetic Racetrack Memory: From Physics to the Cusp of Applications Within a Decade

ShiftsReduce

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