Performance Comparison between Asymmetric Polycrystalline Silicon Gate and TiN Gate Fin-Shaped Field Effect Transistors

Abstract

We report our numerical study on the device performance of an asymmetric polycrystalline silicon (poly-Si) gate fin-shaped field effect transistor (FinFET) and FinFET with TiN metal gate structure. Our numerical simulation revealed that the asymmetric poly-Si FinFET structures and TiN gate FinFET structures exhibits a superior V T tolerance to the conventional FinFET structure with respect to the variation of fin thickness. For instance, the V T tolerance of the asymmetric poly-Si FinFET were 0.02 V while TiN gate FinFET exhibited 0.015 V tolerance for the variation of the fin thickness of 5 nm (from 30 to 35 nm) while the conventional FinFET demonstrates 0.12 V fluctuation for the same variation of the fin thickness. Our numerical simulation revealed that threshold voltage (V T ) can be controlled within À0:1 to þ0:5 V by the varying of doping concentration of the asymmetric poly-Si gate region from 1:0 Â 10 18 to 1:0 Â 10 20 cm À3 .

Impact of Drift Gap, <I>N</I>-Layer, and Deep N<SUP>+</SUP> Sinker on Breakdown Voltage and Saturation Current of Lateral Double-Diffused Metal Oxide Semiconductor Transistor

“…Referring to Figure 8, we see that the proposed device has a maximum impact ionization as low as 2 44 × 10 16 cm −3 s −1 at V DS = 70 V, whereas the conventional one has a value of 6 69 × 10 19 cm −3 s −1 at the same condition, which implies that the proposed LDMOS reduces the carrier generation near the drain at high V GS and V DS to ensure high on-state breakdown voltage. [9][10][11][12][13] Figure 9 shows the simulated device structure and the impact ionization rates at V DS = 30, 50, and 70 V. The high impact ionization spot moves from the gate to the drain due to the high level of current density. As illustrated in Figure 9, the proposed LDMOS reduces the carrier generation near the drain at high V GS and V DS to ensure high on-state breakdown voltage.…”