Performance comparison of KASUMI and hardware architecture optimization of f8 and f9 algorithms for 3g UMTS networks

Yasir, Md.; Wu, Ning; Siddiqui, Aamir Akhtar

doi:10.1109/ibcast.2017.7868088

Cited by 6 publications

(3 citation statements)

References 10 publications

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“…To meet the requirement of the Internet of ings, cryptographic algorithms are frequently optimized for area reduction and high throughput implementation or to achieve a good tradeoff between throughput and speed [12][13][14][15][16][17][18][19][20][21][22][23][24][25]. For low-area design, reutilization/logic optimization methodologies have been widely adopted thereby implementing s-boxes using combinational logic [12][13][14][15][16][17][18][19][20]. A single-round MISTY1 architecture designed for compact implementation is proposed in [20] consisting of only oddround functions, i.e., 2 × FL functions, 1 × FO function, and 1 × 32 bit XOR.…”

Section: Introductionmentioning

confidence: 99%

Design Space Exploration for High-Speed Implementation of the MISTY1 Block Cipher

Hasan

Khizar

Mahmood

et al. 2021

Mathematical Problems in Engineering

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This paper proposes 2 × unrolled high-speed architectures of the MISTY1 block cipher for wireless applications including sensor networks and image encryption. Design space exploration is carried out for 8-round MISTY1 utilizing dual-edge trigger (DET) and single-edge trigger (SET) pipelines to analyze the tradeoff w.r.t. speed/area. The design is primarily based on the optimized implementation of lookup tables (LUTs) for MISTY1 and its core transformation functions. The LUTs are designed by logically formulating S9/S7 s-boxes and FI and {FO + 32-bit XOR} functions with the fine placement of pipelines. Highly efficient and high-speed MISTY1 architectures are thus obtained and implemented on the field-programmable gate array (FPGA), Virtex-7, XC7VX690T. The high-speed/very high-speed MISTY1 architectures acquire throughput values of 25.2/43 Gbps covering an area of 1331/1509 CLB slices, respectively. The proposed MISTY1 architecture outperforms all previous MISTY1 implementations indicating high speed with low area achieving high efficiency value. The proposed architecture had higher efficiency values than the existing AES and Camellia architectures. This signifies the optimizations made for proposed high-speed MISTY1 architectures.

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Section: Introductionmentioning

confidence: 99%

Design Space Exploration for High-Speed Implementation of the MISTY1 Block Cipher

Hasan

Khizar

Mahmood

et al. 2021

Mathematical Problems in Engineering

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show abstract

“…A detailed study has been carried out on the existing hardware designs of MISTY1, KASUMI, AES, SHA-1, CAMELLIA and SAFER [5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22]. The review covered the comparison of performance parameters i.e.…”

Section: Introductionmentioning

confidence: 99%

“…In comparison to high throughput encryption cores, compact designs make use of the logic optimization techniques for transformation functions and s-boxes using combinational logic [5][6][7][8][9][10], [12][13][14][15][16][17][18], [21], [22]. Besides, re-utilization methodologies have also been implemented exploiting the rolling-feature of the architecture.…”

Section: Introductionmentioning

confidence: 99%

Area-Efficient Hardware Architectures of MISTY1 Block Cipher

Yasir¹,

Wu²,

Chen³

et al. 2018

RADIOENGINEERING

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In this paper, state-of-the-art hardware implementations of MISTY1 block cipher are presented for areaconstrained wireless applications. The proposed MISTY1 architectures are characterized of highly optimized transformation functions i.e. FL and {FO-XOR-EKG}. The FL function re-utilizes logic AND-OR-XOR combinations whereas {FO-XOR-EKG} function explores 2 × compact design schemes for s-boxes implementation. A Combined Substitution Unit (CSU) and threshold area implementation are proposed for s-boxes based on Boolean reductions and Common Sub-expression Eliminations (CSEs). Besides, {FO-XOR-EKG} function is designed for manifold operations of FO / FI functions, 32-bit XOR operation and extended key generation thereby reducing the area. Hardware implementations on ASIC 180nm, 1.8V standard library cell realized compact and threshold MISTY1 designs constituting 1853 and 1546 NAND gates with throughput values of 41.6 Mbps and 4.72 Mbps respectively. A comprehensive comparison with existing cryptographic hardware designs establishes that the proposed MISTY1 architectures are the most area-efficient implementations till date.

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Compact and High Speed Architectures of KASUMI Block Cipher

Yasir

Ali

et al. 2018

Wireless Pers Commun

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Performance comparison of KASUMI and hardware architecture optimization of f8 and f9 algorithms for 3g UMTS networks

Cited by 6 publications

References 10 publications

Design Space Exploration for High-Speed Implementation of the MISTY1 Block Cipher

Design Space Exploration for High-Speed Implementation of the MISTY1 Block Cipher

Area-Efficient Hardware Architectures of MISTY1 Block Cipher

Compact and High Speed Architectures of KASUMI Block Cipher

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